aarch64: Represent SQXTUN with RTL operations

This patch removes UNSPEC_SQXTUN and uses organic RTL codes to represent the operation.
SQXTUN is an odd one. It's described in the architecture as "Signed saturating extract Unsigned Narrow".
It's not a straightforward ss_truncate nor a us_truncate.
It is a sort of truncating signed clamp operation with limits derived from the unsigned extrema of the narrow mode:
(truncate:N
  (smin:M
    (smax:M (reg:M) (const_int 0))
    (const_int <unsigned-max-for-mode-N>)))

This patch implements these semantics. I've checked that the vqmovun tests in advsimd-intrinsics.exp
now get constant-folded and still pass validation, so I'm pretty confident in the semantics.

Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (aarch64_sqmovun<mode><vczle><vczbe>):
	Rename to...
	(*aarch64_sqmovun<mode>_insn<vczle><vczbe>): ... This.  Reimplement
	with RTL codes.
	(aarch64_sqmovun<mode> [SD_HSDI]): Reimplement with RTL codes.
	(aarch64_sqxtun2<mode>_le): Likewise.
	(aarch64_sqxtun2<mode>_be): Likewise.
	(aarch64_sqxtun2<mode>): Adjust for the above.
	(aarch64_sqmovun<mode>): New define_expand.
	* config/aarch64/iterators.md (UNSPEC_SQXTUN): Delete.
	(half_mask): New mode attribute.
	* config/aarch64/predicates.md (aarch64_simd_umax_half_mode):
	New predicate.

0 files changed, 0 insertions, 0 deletions