RISC-V: Add sign-extending variants for vmv.x.s.

When the destination register of a vmv.x.s needs to be sign extended to
XLEN we currently emit an sext insn.  Since vmv.x.s performs this
automatically this patch adds two instruction patterns that include
sign_extend for the destination operand.

gcc/ChangeLog:

	* config/riscv/vector-iterators.md: Add VI_QH iterator.
	* config/riscv/autovec-opt.md
	(@pred_extract_first_sextdi<mode>): New vmv.x.s pattern
	that includes sign extension.
	(@pred_extract_first_sextsi<mode>): Dito for SImode.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Ensure
	that no sext insns are present.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Dito.

0 files changed, 0 insertions, 0 deletions