RISC-V: Fine tune RA constraint for narrow instructions

According to RVV ISA, for narrow instructions:

The destination EEW is smaller than the source EEW and the overlap is
in the lowest-numbered part of the source register group.
(e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not).

We should allow narrow instructions partially overlap base on the rule of RVV ISA above
so that we could exploit the useage of vector registers.

Consider these cases:
https://godbolt.org/z/o6sc4eqGj

some cases in LLVM have redundant move instructions,
some cases in LLVM have redundant register spillings.

Now after this patch, GCC can have perfect RA && codegen for different pressure RA cases.

gcc/ChangeLog:

	* config/riscv/vector.md: Fine tune RA constraints.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/narrow_constraint-1.c: New test.
	* gcc.target/riscv/rvv/base/narrow_constraint-10.c: New test.
	* gcc.target/riscv/rvv/base/narrow_constraint-11.c: New test.
	* gcc.target/riscv/rvv/base/narrow_constraint-2.c: New test.
	* gcc.target/riscv/rvv/base/narrow_constraint-3.c: New test.
	* gcc.target/riscv/rvv/base/narrow_constraint-4.c: New test.
	* gcc.target/riscv/rvv/base/narrow_constraint-5.c: New test.
	* gcc.target/riscv/rvv/base/narrow_constraint-6.c: New test.
	* gcc.target/riscv/rvv/base/narrow_constraint-7.c: New test.
	* gcc.target/riscv/rvv/base/narrow_constraint-8.c: New test.
	* gcc.target/riscv/rvv/base/narrow_constraint-9.c: New test.

0 files changed, 0 insertions, 0 deletions