[PATCH v4 2/2] RISC-V: Add support for XCValu extension in CV32E40P

Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: Add the XCValu
	extension.
	* config/riscv/constraints.md: Add builtins for the XCValu
	extension.
	* config/riscv/predicates.md (immediate_register_operand):
	Likewise.
	* config/riscv/corev.def: Likewise.
	* config/riscv/corev.md: Likewise.
	* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
	(RISCV_ATYPE_UHI): Likewise.
	* config/riscv/riscv-ftypes.def: Likewise.
	* config/riscv/riscv.opt: Likewise.
	* config/riscv/riscv.cc (riscv_print_operand): Likewise.
	* doc/extend.texi: Add XCValu documentation.
	* doc/sourcebuild.texi: Likewise.

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp: Add proc for the XCValu extension.
	* gcc.target/riscv/cv-alu-compile.c: New test.
	* gcc.target/riscv/cv-alu-fail-compile-addn.c: New test.
	* gcc.target/riscv/cv-alu-fail-compile-addrn.c: New test.
	* gcc.target/riscv/cv-alu-fail-compile-addun.c: New test.
	* gcc.target/riscv/cv-alu-fail-compile-addurn.c: New test.
	* gcc.target/riscv/cv-alu-fail-compile-clip.c: New test.
	* gcc.target/riscv/cv-alu-fail-compile-clipu.c: New test.
	* gcc.target/riscv/cv-alu-fail-compile-subn.c: New test.
	* gcc.target/riscv/cv-alu-fail-compile-subrn.c: New test.
	* gcc.target/riscv/cv-alu-fail-compile-subun.c: New test.
	* gcc.target/riscv/cv-alu-fail-compile-suburn.c: New test.
	* gcc.target/riscv/cv-alu-fail-compile.c: New test.

0 files changed, 0 insertions, 0 deletions