RISC-V: Implement vec_set and vec_extract.

This implements the vec_set and vec_extract patterns for integer and
floating-point data types.  For vec_set we broadcast the insert value to
a vector register and then perform a vslideup with effective length 1 to
the requested index.

vec_extract is done by sliding down the requested element to index 0
and v(f)mv.[xf].s to a scalar register.

The patch does not include vector-vector extraction which
will be done at a later time.

gcc/ChangeLog:

	* config/riscv/autovec.md (vec_set<mode>): Implement.
	(vec_extract<mode><vel>): Implement.
	* config/riscv/riscv-protos.h (enum insn_type): Add slide insn.
	(emit_vlmax_slide_insn): Declare.
	(emit_nonvlmax_slide_tu_insn): Declare.
	(emit_scalar_move_insn): Export.
	(emit_nonvlmax_integer_move_insn): Export.
	* config/riscv/riscv-v.cc (emit_vlmax_slide_insn): New function.
	(emit_nonvlmax_slide_tu_insn): New function.
	(emit_vlmax_masked_mu_insn): No change.
	(emit_vlmax_integer_move_insn): Export.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c:
	New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-zvfh-run.c:
	New test.

0 files changed, 0 insertions, 0 deletions