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author | Roger Sayle <roger@nextmovesoftware.com> | 2023-07-10 09:04:29 +0100 |
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committer | Roger Sayle <roger@nextmovesoftware.com> | 2023-07-10 09:04:29 +0100 |
commit | 4814b63c3c2326cb5d7baa63882da60ac011bd97 (patch) | |
tree | d695b58c309390bf2e3368bfc8e2505ec8ec8cd4 /libgcc | |
parent | 0cafc3b6272d1dd738e8d7e66e1d8741e08f74d3 (diff) | |
download | gcc-4814b63c3c2326cb5d7baa63882da60ac011bd97.zip gcc-4814b63c3c2326cb5d7baa63882da60ac011bd97.tar.gz gcc-4814b63c3c2326cb5d7baa63882da60ac011bd97.tar.bz2 |
i386: Add AVX512 support for STV of SI/DImode rotation by constant.
Following Uros' suggestion, this patch adds support for AVX512VL's
vpro[lr][dq] instructions to the recently added scalar-to-vector (STV)
enhancements to handle DImode and SImode rotations by a constant.
For the test cases:
unsigned long long rot1(unsigned long long x) {
return (x>>1) | (x<<63);
}
void mem1(unsigned long long *p) {
*p = rot1(*p);
}
with -m32 -O2 -mavx512vl, we currently generate:
rot1: movl 4(%esp), %eax
movl 8(%esp), %edx
movl %eax, %ecx
shrdl $1, %edx, %eax
shrdl $1, %ecx, %edx
ret
mem1: movl 4(%esp), %eax
vmovq (%eax), %xmm0
vpshufd $20, %xmm0, %xmm0
vpsrlq $1, %xmm0, %xmm0
vpshufd $136, %xmm0, %xmm0
vmovq %xmm0, (%eax)
ret
with this patch, we now generate:
rot1: vmovq 4(%esp), %xmm0
vprorq $1, %xmm0, %xmm0
vmovd %xmm0, %eax
vpextrd $1, %xmm0, %edx
ret
mem1: movl 4(%esp), %eax
vmovq (%eax), %xmm0
vprorq $1, %xmm0, %xmm0
vmovq %xmm0, (%eax)
ret
2023-07-10 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/i386/i386-features.cc (compute_convert_gain): Tweak
gains/costs for ROTATE/ROTATERT by integer constant on AVX512VL.
(general_scalar_chain::convert_rotate): On TARGET_AVX512F generate
avx512vl_rolv2di or avx412vl_rolv4si when appropriate.
gcc/testsuite/ChangeLog
* gcc.target/i386/avx512vl-stv-rotatedi-1.c: New test case.
Diffstat (limited to 'libgcc')
0 files changed, 0 insertions, 0 deletions