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author | liuhongt <hongtao.liu@intel.com> | 2023-07-05 13:45:11 +0800 |
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committer | liuhongt <hongtao.liu@intel.com> | 2023-07-06 13:54:25 +0800 |
commit | 37a231cc7594d12ba0822077018aad751a6fb94e (patch) | |
tree | 38b3a4de10d1bb22ea9e29c8b84cf1c8e4605d06 /libgcc | |
parent | 1669fad496ed6cc7ddea142e12af15e0b9f7f3b4 (diff) | |
download | gcc-37a231cc7594d12ba0822077018aad751a6fb94e.zip gcc-37a231cc7594d12ba0822077018aad751a6fb94e.tar.gz gcc-37a231cc7594d12ba0822077018aad751a6fb94e.tar.bz2 |
Disparage slightly for the alternative which move DFmode between SSE_REGS and GENERAL_REGS.
For testcase
void __cond_swap(double* __x, double* __y) {
bool __r = (*__x < *__y);
auto __tmp = __r ? *__x : *__y;
*__y = __r ? *__y : *__x;
*__x = __tmp;
}
GCC-14 with -O2 and -march=x86-64 options generates the following code:
__cond_swap(double*, double*):
movsd xmm1, QWORD PTR [rdi]
movsd xmm0, QWORD PTR [rsi]
comisd xmm0, xmm1
jbe .L2
movq rax, xmm1
movapd xmm1, xmm0
movq xmm0, rax
.L2:
movsd QWORD PTR [rsi], xmm1
movsd QWORD PTR [rdi], xmm0
ret
rax is used to save and restore DFmode value. In RA both GENERAL_REGS
and SSE_REGS cost zero since we didn't disparage the
alternative in movdf_internal pattern, according to register
allocation order, GENERAL_REGS is allocated. The patch add ? for
alternative (r,v) and (v,r) just like we did for movsf/hf/bf_internal
pattern, after that we get optimal RA.
__cond_swap:
.LFB0:
.cfi_startproc
movsd (%rdi), %xmm1
movsd (%rsi), %xmm0
comisd %xmm1, %xmm0
jbe .L2
movapd %xmm1, %xmm2
movapd %xmm0, %xmm1
movapd %xmm2, %xmm0
.L2:
movsd %xmm1, (%rsi)
movsd %xmm0, (%rdi)
ret
gcc/ChangeLog:
PR target/110170
* config/i386/i386.md (movdf_internal): Disparage slightly for
2 alternatives (r,v) and (v,r) by adding constraint modifier
'?'.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr110170-3.c: New test.
Diffstat (limited to 'libgcc')
0 files changed, 0 insertions, 0 deletions