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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-10-21 04:28:21 +0000 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-10-22 02:21:05 +0000 |
| commit | 11f50716eee812c4a27b66f894e7f3ed0c870534 (patch) | |
| tree | 1ca7a66ed268c8e45e2d6ba960dcedaa5e4c80fe /libgcc | |
| parent | f232391ae6dda94d8a37fc69a3ced7ab6cffcb8e (diff) | |
| download | gcc-11f50716eee812c4a27b66f894e7f3ed0c870534.zip gcc-11f50716eee812c4a27b66f894e7f3ed0c870534.tar.gz gcc-11f50716eee812c4a27b66f894e7f3ed0c870534.tar.bz2 | |
RISC-V: Prohibit combination of 'E' and 'H'
According to the ratified privileged specification (version 20211203),
it says:
> The hypervisor extension depends on an "I" base integer ISA with 32 x
> registers (RV32I or RV64I), not RV32E, which has only 16 x registers.
Also in the latest draft, it also prohibits RV64E with the 'H' extension.
This commit prohibits the combination of 'E' and 'H' extensions.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
Prohibit 'E' and 'H' combinations.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-26.c: New test.
Diffstat (limited to 'libgcc')
0 files changed, 0 insertions, 0 deletions