RISC-V: Add test cases for insn does not satisfy its constraints [PR114714]

We have one ICE when RVV register overlap is enabled.  We reverted this
feature as it is in stage 4 and there is no much time to figure a better
solution for this.  Thus, for now add the related test cases which will
trigger ICE when register overlap enabled.

This will gate the RVV register overlap support in GCC-15.

	PR target/114714

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/pr114714-1.C: New test.
	* g++.target/riscv/rvv/base/pr114714-2.C: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-by: Kito Cheng <kito.cheng@sifive.com>

0 files changed, 0 insertions, 0 deletions