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| author | H.J. Lu <hjl.tools@gmail.com> | 2024-04-12 15:42:12 -0700 |
|---|---|---|
| committer | H.J. Lu <(no_default)> | 2024-04-15 04:21:17 -0700 |
| commit | a3281dd0f4b46c16ec1192ad411c0a96e6d086eb (patch) | |
| tree | fb168726405fd91ad16a5269060bce39c65f6580 /libgcc | |
| parent | 85002f8085c25bb3e74ab013581a74e7c7ae006b (diff) | |
| download | gcc-a3281dd0f4b46c16ec1192ad411c0a96e6d086eb.zip gcc-a3281dd0f4b46c16ec1192ad411c0a96e6d086eb.tar.gz gcc-a3281dd0f4b46c16ec1192ad411c0a96e6d086eb.tar.bz2 | |
x86: Allow TImode offsettable memory only with 8-bit constant
The x86 instruction size limit is 15 bytes. If a NDD instruction has
a segment prefix byte, a 4-byte opcode prefix, a MODRM byte, a SIB byte,
a 4-byte displacement and a 4-byte immediate, adding an address size
prefix will exceed the size limit. Change TImode ADD, AND, OR and XOR
to allow offsettable memory only with 8-bit signed integer constant,
which is encoded with a 1-byte immediate, if the address size prefix
is used.
gcc/
PR target/114696
* config/i386/i386.md (isa): Add apx_ndd_64.
(enabled): Likewise.
(*add<dwi>3_doubleword): Change rjO to r,ro,jO with 8-bit
signed integer constant and enable jO only for apx_ndd_64.
(*add<dwi>3_doubleword_cc_overflow_1): Likewise.
(*and<dwi>3_doubleword): Likewise.
(*<code><dwi>3_doubleword): Likewise.
gcc/testsuite/
PR target/114696
* gcc.target/i386/apx-ndd-x32-2a.c: New test.
* gcc.target/i386/apx-ndd-x32-2b.c: Likewise.
* gcc.target/i386/apx-ndd-x32-2c.c: Likewise.
* gcc.target/i386/apx-ndd-x32-2d.c: Likewise.
Diffstat (limited to 'libgcc')
0 files changed, 0 insertions, 0 deletions