RISC-V: Allow RVV intrinsic when function target("arch=+v")

This patch would like to allow the RVV intrinsic when function is
attributed as target("arch=+v") and build with rv64gc.  For example:

vint32m1_t
__attribute__((target("arch=+v")))
test_1 (vint32m1_t a, vint32m1_t b, size_t vl)
{
  return __riscv_vadd_vv_i32m1 (a, b, vl);
}

build with -march=rv64gc -mabi=lp64d -O3, we will have asm like below:
test_1:
  .option push
  .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_\
zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
  vsetvli zero,a0,e32,m1,ta,ma
  vadd.vv v8,v8,v9
  ret

The riscv_vector.h must be included when leverage intrinisc type(s) and
API(s).  And the scope of this attribute should not excced the function
body.  Meanwhile, to make rvv types and API(s) available for this attribute,
include riscv_vector.h will not report error for now if v is not present
in march.

Below test are passed for this patch:
* The riscv fully regression test.

gcc/ChangeLog:

	* config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Remove error
	when V is disabled and init the RVV types and intrinic APIs.
	* config/riscv/riscv-vector-builtins.cc (expand_builtin): Report
	error if V ext is disabled.
	* config/riscv/riscv.cc (riscv_return_value_is_vector_type_p):
	Ditto.
	(riscv_arguments_is_vector_type_p): Ditto.
	(riscv_vector_cc_function_p): Ditto.
	* config/riscv/riscv_vector.h: Remove error if V is disable.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pragma-1.c: Remove.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-1.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-2.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-4.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-5.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-6.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions