Merge from trunk revision 254059.

From-SVN: r254062

23 files changed, 370 insertions, 41 deletions

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index b548922..f137fdf 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,30 +1,75 @@
+2017-10-23  Sebastian Perta  <sebastian.perta@renesas.com>
+
+	* config/rl78/subdi3.S: New assembly file.
+	* config/rl78/t-rl78: Added subdi3.S to LIB2ADD.
+
+2017-10-13  Sebastian Perta  <sebastian.perta@renesas.com>
+
+	* config/rl78/adddi3.S: New assembly file.
+	* config/rl78/t-rl78: Added adddi3.S to LIB2ADD.
+
+2017-10-13  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/82274
+	* libgcc2.c (__mulvDI3): If both operands have
+	the same highpart of -1 and the topmost bit of lowpart is 0,
+	multiplication overflows even if both lowparts are 0.
+
+2017-09-28  James Bowman  <james.bowman@ftdichip.com>
+
+	* config/ft32/crti-hw.S: Add watchdog vector, FT930 IRQ support.
+
+2017-09-26  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/microblaze/crti.S, config/microblaze/crtn.S,
+	config/microblaze/divsi3.S, config/microblaze/moddi3.S,
+	config/microblaze/modsi3.S, config/microblaze/muldi3_hard.S,
+	config/microblaze/mulsi3.S,
+	config/microblaze/stack_overflow_exit.S,
+	config/microblaze/udivsi3.S, config/microblaze/umodsi3.S,
+	config/pa/milli64.S: Add .note.GNU-stack section.
+
+2017-09-23  Daniel Santos  <daniel.santos@pobox.com>
+
+	* configure.ac: Add Check for HAVE_AS_AVX.
+	* config.in: Regenerate.
+	* configure: Likewise.
+	* config/i386/i386-asm.h: Include auto-target.h from libgcc.
+	(SSE_SAVE, SSE_RESTORE): Emit .byte sequence for !HAVE_AS_AVX.
+	Correct out-of-date comments.
+
+2017-09-20  Sebastian Peryt  <sebastian.peryt@intel.com>
+
+	* config/i386/cpuinfo.h (processor_types): Add INTEL_KNM.
+	* config/i386/cpuinfo.c (get_intel_cpu): Detect Knights Mill.
+
 2017-09-17  Daniel Santos  <daniel.santos@pobox.com>
 
-	config/i386/i386-asm.h (PASTE2): New macro.
+	* config/i386/i386-asm.h (PASTE2): New macro.
 	(ASMNAME): Modify to use PASTE2.
 	(MS2SYSV_STUB_PREFIX): New macro for isa prefix.
 	(MS2SYSV_STUB_BEGIN, MS2SYSV_STUB_END): New macros for stub headers.
-	config/i386/resms64.S: Rename to a header file, use MS2SYSV_STUB_BEGIN
+	* config/i386/resms64.S: Rename to a header file, use MS2SYSV_STUB_BEGIN
 	instead of HIDDEN_FUNC and MS2SYSV_STUB_END instead of FUNC_END.
-	config/i386/resms64f.S: Likewise.
-	config/i386/resms64fx.S: Likewise.
-	config/i386/resms64x.S: Likewise.
-	config/i386/savms64.S: Likewise.
-	config/i386/savms64f.S: Likewise.
-	config/i386/avx_resms64.S: New file that only defines a macro and
+	* config/i386/resms64f.S: Likewise.
+	* config/i386/resms64fx.S: Likewise.
+	* config/i386/resms64x.S: Likewise.
+	* config/i386/savms64.S: Likewise.
+	* config/i386/savms64f.S: Likewise.
+	* config/i386/avx_resms64.S: New file that only defines a macro and
 	includes it's corresponding header file.
-	config/i386/avx_resms64f.S: Likewise.
-	config/i386/avx_resms64fx.S: Likewise.
-	config/i386/avx_resms64x.S: Likewise.
-	config/i386/avx_savms64.S: Likewise.
-	config/i386/avx_savms64f.S: Likewise.
-	config/i386/sse_resms64.S: Likewise.
-	config/i386/sse_resms64f.S: Likewise.
-	config/i386/sse_resms64fx.S: Likewise.
-	config/i386/sse_resms64x.S: Likewise.
-	config/i386/sse_savms64.S: Likewise.
-	config/i386/sse_savms64f.S: Likewise.
-	config/i386/t-msabi: Modified to add avx and sse versions of stubs.
+	* config/i386/avx_resms64f.S: Likewise.
+	* config/i386/avx_resms64fx.S: Likewise.
+	* config/i386/avx_resms64x.S: Likewise.
+	* config/i386/avx_savms64.S: Likewise.
+	* config/i386/avx_savms64f.S: Likewise.
+	* config/i386/sse_resms64.S: Likewise.
+	* config/i386/sse_resms64f.S: Likewise.
+	* config/i386/sse_resms64fx.S: Likewise.
+	* config/i386/sse_resms64x.S: Likewise.
+	* config/i386/sse_savms64.S: Likewise.
+	* config/i386/sse_savms64f.S: Likewise.
+	* config/i386/t-msabi: Modified to add avx and sse versions of stubs.
 
 2017-09-01  Olivier Hainque  <hainque@adacore.com>
 
diff --git a/libgcc/config.in b/libgcc/config.in
index 7de22ee..f9fb253 100644
--- a/libgcc/config.in
+++ b/libgcc/config.in
@@ -1,5 +1,8 @@
 /* config.in.  Generated from configure.ac by autoheader.  */
 
+/* Define to 1 if the assembler supports AVX. */
+#undef HAVE_AS_AVX
+
 /* Define to 1 if the target assembler supports thread-local storage. */
 #undef HAVE_CC_TLS
 
diff --git a/libgcc/config/ft32/crti-hw.S b/libgcc/config/ft32/crti-hw.S
index c2951fc..8ee1d38 100644
--- a/libgcc/config/ft32/crti-hw.S
+++ b/libgcc/config/ft32/crti-hw.S
@@ -1,8 +1,8 @@
 .global _start
 _start:
 # START Interrupt Vector Table [[
-        jmp     __PMSIZE-4
-        jmp     watchdog_init
+        jmp     __PMSIZE-4         # RESET Vector
+        jmp     interrupt_33       # Watchdog reset vector
         jmp     interrupt_0
         jmp     interrupt_1
         jmp     interrupt_2
@@ -35,24 +35,29 @@ _start:
         jmp     interrupt_29
         jmp     interrupt_30
         jmp     interrupt_31
-        jmp     __PMSIZE-8
+        jmp     __PMSIZE-8         # Interrupt vector 32 (NMI)
 # ]] END Interrupt Vector Table
 
 codestart:
         jmp    init
-        
+
 .global _exithook
 _exithook:               # Debugger uses '_exithook' at 0x90 to catch program exit
         return
-        
-watchdog_init:
-        ldk	$r0,1
+
 init:
         ldk     $sp,__RAMSIZE
         # Disable all interrupts
-        ldk     $r4,0x80
-        sta.b   0x100e3,$r4
-        
+        lda   $r1,0x10000
+        lshr  $r1,$r1,20
+        cmp   $r1,0x90
+        ldk   $r1,0x100e3   # FT900 IRQ Control Register
+        jmpc  z,1f
+        ldk   $r1,0x10123   # FT930 IRQ Control Register
+1:
+        ldk   $r4,0x80
+        sti.b $r1,0,$r4
+
         # Initialize DATA by copying from program memory
         ldk.l   $r4,__data_load_start
         ldk.l   $r1,__data_load_end
@@ -139,6 +144,7 @@ interrupt_\i:
         inth    30
         inth    31
         inth    32
+        inth    33
 
         # On entry: r0, already saved, holds the handler function
 interrupt_common:
@@ -182,7 +188,7 @@ nullvector:
 .section .data
 .global vector_table
 vector_table:
-        .rept 33
+        .rept 34
                 .long   nullvector
         .endr
 
diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c
index b008fb6..c2ab8be 100644
--- a/libgcc/config/i386/cpuinfo.c
+++ b/libgcc/config/i386/cpuinfo.c
@@ -137,6 +137,10 @@ get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
 	      /* Knights Landing.  */
 	      __cpu_model.__cpu_type = INTEL_KNL;
 	      break;
+	    case 0x85:
+	      /* Knights Mill. */
+	      __cpu_model.__cpu_type = INTEL_KNM;
+	      break;
 	    case 0x1a:
 	    case 0x1e:
 	    case 0x1f:
diff --git a/libgcc/config/i386/cpuinfo.h b/libgcc/config/i386/cpuinfo.h
index 872b45e..3978401 100644
--- a/libgcc/config/i386/cpuinfo.h
+++ b/libgcc/config/i386/cpuinfo.h
@@ -47,6 +47,7 @@ enum processor_types
   AMD_BTVER1,
   AMD_BTVER2,  
   AMDFAM17H,
+  INTEL_KNM,
   CPU_TYPE_MAX
 };
 
diff --git a/libgcc/config/i386/i386-asm.h b/libgcc/config/i386/i386-asm.h
index 424e0f7..aad1a75 100644
--- a/libgcc/config/i386/i386-asm.h
+++ b/libgcc/config/i386/i386-asm.h
@@ -26,6 +26,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #ifndef I386_ASM_H
 #define I386_ASM_H
 
+#include "auto-target.h"
 #include "auto-host.h"
 
 #define PASTE2(a, b) PASTE2a(a, b)
@@ -69,13 +70,15 @@ ASMNAME(fn):
 
 #ifdef MS2SYSV_STUB_AVX
 # define MS2SYSV_STUB_PREFIX __avx_
-# define MOVAPS vmovaps
+# ifdef HAVE_AS_AVX
+#  define MOVAPS vmovaps
+# endif
 #elif defined(MS2SYSV_STUB_SSE)
 # define MS2SYSV_STUB_PREFIX __sse_
 # define MOVAPS movaps
 #endif
 
-#if defined (MS2SYSV_STUB_PREFIX) && defined (MOVAPS)
+#ifdef MS2SYSV_STUB_PREFIX
 
 # define MS2SYSV_STUB_BEGIN(base_name) \
 	HIDDEN_FUNC(PASTE2(MS2SYSV_STUB_PREFIX, base_name))
@@ -83,8 +86,10 @@ ASMNAME(fn):
 # define MS2SYSV_STUB_END(base_name) \
 	FUNC_END(PASTE2(MS2SYSV_STUB_PREFIX, base_name))
 
-/* Save SSE registers 6-15. off is the offset of rax to get to xmm6.  */
-# define SSE_SAVE		   \
+/* If expanding for sse or avx and we have assembler support.  */
+# ifdef MOVAPS
+/* Save SSE registers 6-15 using rax as the base address.  */
+#  define SSE_SAVE		   \
 	MOVAPS %xmm15,-0x30(%rax); \
 	MOVAPS %xmm14,-0x20(%rax); \
 	MOVAPS %xmm13,-0x10(%rax); \
@@ -96,8 +101,8 @@ ASMNAME(fn):
 	MOVAPS %xmm7,  0x50(%rax); \
 	MOVAPS %xmm6,  0x60(%rax)
 
-/* Restore SSE registers 6-15. off is the offset of rsi to get to xmm6.  */
-# define SSE_RESTORE		    \
+/* Restore SSE registers 6-15 using rsi as the base address.  */
+#  define SSE_RESTORE		    \
 	MOVAPS -0x30(%rsi), %xmm15; \
 	MOVAPS -0x20(%rsi), %xmm14; \
 	MOVAPS -0x10(%rsi), %xmm13; \
@@ -108,6 +113,31 @@ ASMNAME(fn):
 	MOVAPS  0x40(%rsi), %xmm8 ; \
 	MOVAPS  0x50(%rsi), %xmm7 ; \
 	MOVAPS  0x60(%rsi), %xmm6
-
-#endif /* defined (MS2SYSV_STUB_ISA) && defined (MOVAPS) */
+# else /* MOVAPS */
+/* If the assembler doesn't support AVX then directly emit machine code
+   for the instructions above.  */
+#  define SSE_SAVE							     \
+	.byte 0xc5, 0x78, 0x29, 0x78, 0xd0; /* vmovaps %xmm15,-0x30(%rax) */ \
+	.byte 0xc5, 0x78, 0x29, 0x70, 0xe0; /* vmovaps %xmm14,-0x20(%rax) */ \
+	.byte 0xc5, 0x78, 0x29, 0x68, 0xf0; /* vmovaps %xmm13,-0x10(%rax) */ \
+	.byte 0xc5, 0x78, 0x29, 0x20;       /* vmovaps %xmm12,     (%rax) */ \
+	.byte 0xc5, 0x78, 0x29, 0x58, 0x10; /* vmovaps %xmm11, 0x10(%rax) */ \
+	.byte 0xc5, 0x78, 0x29, 0x50, 0x20; /* vmovaps %xmm10, 0x20(%rax) */ \
+	.byte 0xc5, 0x78, 0x29, 0x48, 0x30; /* vmovaps %xmm9,  0x30(%rax) */ \
+	.byte 0xc5, 0x78, 0x29, 0x40, 0x40; /* vmovaps %xmm8,  0x40(%rax) */ \
+	.byte 0xc5, 0xf8, 0x29, 0x78, 0x50; /* vmovaps %xmm7,  0x50(%rax) */ \
+	.byte 0xc5, 0xf8, 0x29, 0x70, 0x60; /* vmovaps %xmm6,  0x60(%rax) */
+#  define SSE_RESTORE							     \
+	.byte 0xc5, 0x78, 0x28, 0x7e, 0xd0; /* vmovaps -0x30(%rsi),%xmm15 */ \
+	.byte 0xc5, 0x78, 0x28, 0x76, 0xe0; /* vmovaps -0x20(%rsi),%xmm14 */ \
+	.byte 0xc5, 0x78, 0x28, 0x6e, 0xf0; /* vmovaps -0x10(%rsi),%xmm13 */ \
+	.byte 0xc5, 0x78, 0x28, 0x26;       /* vmovaps      (%rsi),%xmm12 */ \
+	.byte 0xc5, 0x78, 0x28, 0x5e, 0x10; /* vmovaps  0x10(%rsi),%xmm11 */ \
+	.byte 0xc5, 0x78, 0x28, 0x56, 0x20; /* vmovaps  0x20(%rsi),%xmm10 */ \
+	.byte 0xc5, 0x78, 0x28, 0x4e, 0x30; /* vmovaps  0x30(%rsi),%xmm9  */ \
+	.byte 0xc5, 0x78, 0x28, 0x46, 0x40; /* vmovaps  0x40(%rsi),%xmm8  */ \
+	.byte 0xc5, 0xf8, 0x28, 0x7e, 0x50; /* vmovaps  0x50(%rsi),%xmm7  */ \
+	.byte 0xc5, 0xf8, 0x28, 0x76, 0x60; /* vmovaps  0x60(%rsi),%xmm6  */
+# endif /* MOVAPS */
+#endif /* MS2SYSV_STUB_PREFIX */
 #endif /* I386_ASM_H */
diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
index 61626e2..7356163 100644
--- a/libgcc/config/microblaze/crti.S
+++ b/libgcc/config/microblaze/crti.S
@@ -24,6 +24,12 @@
    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
    <http://www.gnu.org/licenses/>.  */
 
+/* An executable stack is *not* required for these functions.  */
+#ifdef __linux__
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
     .section .init, "ax"
     .global __init
 
diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
index 3b9bf7e..c784ed4 100644
--- a/libgcc/config/microblaze/crtn.S
+++ b/libgcc/config/microblaze/crtn.S
@@ -24,6 +24,12 @@
    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
    <http://www.gnu.org/licenses/>.  */
 
+/* An executable stack is *not* required for these functions.  */
+#ifdef __linux__
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
     .section .init, "ax"
     lw      r15, r0, r1
     rtsd    r15, 8 
diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
index 42f9cb2..0cd14b3 100644
--- a/libgcc/config/microblaze/divsi3.S
+++ b/libgcc/config/microblaze/divsi3.S
@@ -32,6 +32,12 @@
 # 
 #######################################
 	
+/* An executable stack is *not* required for these functions.  */
+#ifdef __linux__
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
 	.globl	__divsi3
 	.ent	__divsi3
 	.type	__divsi3,@function
diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
index bcea079..7d2a31d 100644
--- a/libgcc/config/microblaze/moddi3.S
+++ b/libgcc/config/microblaze/moddi3.S
@@ -30,6 +30,12 @@
 #######################################
 
 
+/* An executable stack is *not* required for these functions.  */
+#ifdef __linux__
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
 	.globl	__moddi3
 	.ent	__moddi3
 __moddi3:
diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
index eb671a1..118b18d 100644
--- a/libgcc/config/microblaze/modsi3.S
+++ b/libgcc/config/microblaze/modsi3.S
@@ -32,6 +32,12 @@
 # 
 #######################################
 
+/* An executable stack is *not* required for these functions.  */
+#ifdef __linux__
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
 	.globl	__modsi3
 	.ent	__modsi3
 	.type	__modsi3,@function
diff --git a/libgcc/config/microblaze/muldi3_hard.S b/libgcc/config/microblaze/muldi3_hard.S
index f2188c6..d9f1806 100644
--- a/libgcc/config/microblaze/muldi3_hard.S
+++ b/libgcc/config/microblaze/muldi3_hard.S
@@ -47,6 +47,12 @@
 #
 #######################################
 
+/* An executable stack is *not* required for these functions.  */
+#ifdef __linux__
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
 	.globl	muldi3_hardproc
 	.ent	muldi3_hardproc
 muldi3_hardproc:
diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
index f126b56..3d33522 100644
--- a/libgcc/config/microblaze/mulsi3.S
+++ b/libgcc/config/microblaze/mulsi3.S
@@ -32,6 +32,12 @@
 # 
 #######################################
 
+/* An executable stack is *not* required for these functions.  */
+#ifdef __linux__
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
 	.globl	__mulsi3
 	.ent	__mulsi3
 	.type	__mulsi3,@function
diff --git a/libgcc/config/microblaze/stack_overflow_exit.S b/libgcc/config/microblaze/stack_overflow_exit.S
index 63319de..5f6be94 100644
--- a/libgcc/config/microblaze/stack_overflow_exit.S
+++ b/libgcc/config/microblaze/stack_overflow_exit.S
@@ -33,6 +33,12 @@
 # 
 #######################################
 
+/* An executable stack is *not* required for these functions.  */
+#ifdef __linux__
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
 	.globl	_stack_overflow_error
 	.data
 	.align	2
diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
index 2e08fb2..f01c027 100644
--- a/libgcc/config/microblaze/udivsi3.S
+++ b/libgcc/config/microblaze/udivsi3.S
@@ -32,6 +32,12 @@
 # 
 #######################################
 	
+/* An executable stack is *not* required for these functions.  */
+#ifdef __linux__
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
 	.globl	__udivsi3
 	.ent	__udivsi3
 	.type	__udivsi3,@function
diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
index b230a8c..a91eae7 100644
--- a/libgcc/config/microblaze/umodsi3.S
+++ b/libgcc/config/microblaze/umodsi3.S
@@ -32,6 +32,12 @@
 # 
 #######################################
 	
+/* An executable stack is *not* required for these functions.  */
+#ifdef __linux__
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
 	.globl	__umodsi3
 	.ent	__umodsi3
 	.type	__umodsi3,@function
diff --git a/libgcc/config/pa/milli64.S b/libgcc/config/pa/milli64.S
index cfd4d83..4690dd1 100644
--- a/libgcc/config/pa/milli64.S
+++ b/libgcc/config/pa/milli64.S
@@ -25,6 +25,12 @@ a copy of the GCC Runtime Library Exception along with this program;
 see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 <http://www.gnu.org/licenses/>.  */
 
+/* An executable stack is *not* required for these functions.  */
+#if defined(__ELF__) && defined(__linux__)
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
 #ifdef pa64
         .level  2.0w
 #endif
diff --git a/libgcc/config/rl78/adddi3.S b/libgcc/config/rl78/adddi3.S
new file mode 100644
index 0000000..c805055
--- /dev/null
+++ b/libgcc/config/rl78/adddi3.S
@@ -0,0 +1,58 @@
+;   Copyright (C) 2017 Free Software Foundation, Inc.
+;   Contributed by Sebastian Perta.
+;
+; This file is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published by the
+; Free Software Foundation; either version 3, or (at your option) any
+; later version.
+;
+; This file is distributed in the hope that it will be useful, but
+; WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+; General Public License for more details.
+;
+; Under Section 7 of GPL version 3, you are granted additional
+; permissions described in the GCC Runtime Library Exception, version
+; 3.1, as published by the Free Software Foundation.
+;
+; You should have received a copy of the GNU General Public License and
+; a copy of the GCC Runtime Library Exception along with this program;
+; see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+; <http://www.gnu.org/licenses/>.
+
+
+#include "vregs.h"
+
+    .text
+
+START_FUNC ___adddi3
+
+    movw  hl, sp       ; use HL-based addressing (allows for direct addw)
+
+    movw  ax, [hl+4]
+    addw  ax, [hl+12]
+    movw  r8, ax
+
+    mov   a, [hl+6]    ; middle bytes of the result are determined using 8-bit
+    addc  a, [hl+14]   ; ADDC insns which both account for and update the carry bit
+    mov   r10, a       ; (no ADDWC instruction is available)
+    mov   a, [hl+7]
+    addc  a, [hl+15]
+    mov   r11, a
+
+    mov   a, [hl+8]
+    addc  a, [hl+16]
+    mov   r12, a
+    mov   a, [hl+9]
+    addc  a, [hl+17]
+    mov   r13, a
+
+    movw  ax, [hl+10]
+    sknc               ; account for the possible carry from the
+    incw  ax           ; latest 8-bit operation
+    addw  ax, [hl+18]
+    movw  r14, ax
+
+    ret
+
+END_FUNC ___adddi3
diff --git a/libgcc/config/rl78/subdi3.S b/libgcc/config/rl78/subdi3.S
new file mode 100644
index 0000000..f6fcaba
--- /dev/null
+++ b/libgcc/config/rl78/subdi3.S
@@ -0,0 +1,58 @@
+;   Copyright (C) 2017 Free Software Foundation, Inc.
+;   Contributed by Sebastian Perta.
+;
+; This file is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published by the
+; Free Software Foundation; either version 3, or (at your option) any
+; later version.
+;
+; This file is distributed in the hope that it will be useful, but
+; WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+; General Public License for more details.
+;
+; Under Section 7 of GPL version 3, you are granted additional
+; permissions described in the GCC Runtime Library Exception, version
+; 3.1, as published by the Free Software Foundation.
+;
+; You should have received a copy of the GNU General Public License and
+; a copy of the GCC Runtime Library Exception along with this program;
+; see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+; <http://www.gnu.org/licenses/>.
+
+
+#include "vregs.h"
+
+    .text
+
+START_FUNC ___subdi3
+
+    movw  hl, sp       ; use HL-based addressing (allows for direct subw)
+
+    movw  ax, [hl+4]
+    subw  ax, [hl+12]
+    movw  r8, ax
+
+    mov   a, [hl+6]    ; middle bytes of the result are determined using 8-bit
+    subc  a, [hl+14]   ; SUBC insns which both account for and update the carry bit
+    mov   r10, a       ; (no SUBWC instruction is available)
+    mov   a, [hl+7]
+    subc  a, [hl+15]
+    mov   r11, a
+
+    mov   a, [hl+8]
+    subc  a, [hl+16]
+    mov   r12, a
+    mov   a, [hl+9]
+    subc  a, [hl+17]
+    mov   r13, a
+
+    movw  ax, [hl+10]
+    sknc               ; account for the possible carry from the
+    decw  ax           ; latest 8-bit operation
+    subw  ax, [hl+18]
+    movw  r14, ax
+
+    ret
+
+END_FUNC ___subdi3
diff --git a/libgcc/config/rl78/t-rl78 b/libgcc/config/rl78/t-rl78
index 6e48a85..e035d58 100644
--- a/libgcc/config/rl78/t-rl78
+++ b/libgcc/config/rl78/t-rl78
@@ -30,7 +30,9 @@ LIB2ADD = \
 	$(srcdir)/config/rl78/bit-count.S \
 	$(srcdir)/config/rl78/fpbit-sf.S \
 	$(srcdir)/config/rl78/fpmath-sf.S \
-	$(srcdir)/config/rl78/cmpsi2.S
+	$(srcdir)/config/rl78/cmpsi2.S \
+	$(srcdir)/config/rl78/adddi3.S \
+	$(srcdir)/config/rl78/subdi3.S
 
 LIB2FUNCS_EXCLUDE = _clzhi2 _clzsi2 _ctzhi2 _ctzsi2 \
   _popcounthi2 _popcountsi2 \
diff --git a/libgcc/configure b/libgcc/configure
index 15d34b2..63c50c0 100644
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -5212,6 +5212,45 @@ if test "$enable_tls $gcc_cv_use_emutls" = "yes yes"; then
 fi
 
 
+
+
+case "${target}" in
+i[34567]86-*-* | x86_64-*-*)
+  { $as_echo "$as_me:${as_lineno-$LINENO}: checking if the assembler supports AVX" >&5
+$as_echo_n "checking if the assembler supports AVX... " >&6; }
+if test "${libgcc_cv_as_avx+set}" = set; then :
+  $as_echo_n "(cached) " >&6
+else
+
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+asm("vzeroupper");
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  libgcc_cv_as_avx=yes
+else
+  libgcc_cv_as_avx=no
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_as_avx" >&5
+$as_echo "$libgcc_cv_as_avx" >&6; }
+  if test x$libgcc_cv_as_avx = xyes; then
+
+$as_echo "#define HAVE_AS_AVX 1" >>confdefs.h
+
+  fi
+  ;;
+esac
+
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for init priority support" >&5
 $as_echo_n "checking for init priority support... " >&6; }
 if test "${libgcc_cv_init_priority+set}" = set; then :
diff --git a/libgcc/configure.ac b/libgcc/configure.ac
index da49971..dd60b01 100644
--- a/libgcc/configure.ac
+++ b/libgcc/configure.ac
@@ -506,6 +506,22 @@ if test "$enable_tls $gcc_cv_use_emutls" = "yes yes"; then
 fi
 AC_SUBST(set_use_emutls)
 
+dnl Check if as supports AVX instructions.
+AC_DEFUN([LIBGCC_CHECK_AS_AVX], [
+case "${target}" in
+i[[34567]]86-*-* | x86_64-*-*)
+  AC_CACHE_CHECK([if the assembler supports AVX], libgcc_cv_as_avx, [
+    AC_TRY_COMPILE([], [asm("vzeroupper");],
+		   [libgcc_cv_as_avx=yes], [libgcc_cv_as_avx=no])
+  ])
+  if test x$libgcc_cv_as_avx = xyes; then
+    AC_DEFINE(HAVE_AS_AVX, 1, [Define to 1 if the assembler supports AVX.])
+  fi
+  ;;
+esac])
+LIBGCC_CHECK_AS_AVX
+
+dnl Check if as supports RTM instructions.
 AC_CACHE_CHECK(for init priority support, libgcc_cv_init_priority, [
 AC_COMPILE_IFELSE([AC_LANG_PROGRAM(,
   [[void ip (void) __attribute__ ((constructor (1)));]])],
diff --git a/libgcc/libgcc2.c b/libgcc/libgcc2.c
index 5d3c69f..83f865a 100644
--- a/libgcc/libgcc2.c
+++ b/libgcc/libgcc2.c
@@ -375,7 +375,8 @@ __mulvDI3 (DWtype u, DWtype v)
 		}
 	      else
 		{
-		  if (uu.s.high == (Wtype) -1 && vv.s.high == (Wtype) - 1)
+		  if ((uu.s.high & vv.s.high) == (Wtype) -1
+		      && (uu.s.low | vv.s.low) != 0)
 		    {
 		      DWunion ww = {.ll = (UDWtype) (UWtype) uu.s.low
 				    * (UDWtype) (UWtype) vv.s.low};