diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2020-01-25 12:43:28 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2020-01-27 15:13:01 +0000 |
| commit | c15893df6eafc32efd6184379dd7f02c36da7d12 (patch) | |
| tree | 114a7cc1ef8219437dde14ca6b64724c5b99d063 /libgcc/libgcov-profiler.c | |
| parent | e2a14becd6bdc68e1d2fbe084079f7472434488e (diff) | |
| download | gcc-c15893df6eafc32efd6184379dd7f02c36da7d12.zip gcc-c15893df6eafc32efd6184379dd7f02c36da7d12.tar.gz gcc-c15893df6eafc32efd6184379dd7f02c36da7d12.tar.bz2 | |
aarch64: Add vector/vector vec_extract patterns [PR92822]
Part of the problem in this PR is that we don't provide patterns
to extract a 64-bit vector from one half of a 128-bit vector.
Adding them fixes:
FAIL: gcc.target/aarch64/fmul_intrinsic_1.c scan-assembler-times fmul\\td[0-9]+, d[0-9]+, d[0-9]+ 1
FAIL: gcc.target/aarch64/fmul_intrinsic_1.c scan-assembler-times fmul\\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.d\\[[0-9]+\\] 3
The 2s failures need target-independent changes, after which they rely
on these patterns too.
2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
PR target/92822
* config/aarch64/aarch64-simd.md (aarch64_get_half<mode>): New
expander.
(@aarch64_split_simd_mov<mode>): Use it.
(aarch64_simd_mov_from_<mode>low): Add a GPR alternative.
Leave the vec_extract patterns to handle 2-element vectors.
(aarch64_simd_mov_from_<mode>high): Likewise.
(vec_extract<VQMOV_NO2E:mode><Vhalf>): New expander.
(vec_extractv2dfv1df): Likewise.
Diffstat (limited to 'libgcc/libgcov-profiler.c')
0 files changed, 0 insertions, 0 deletions