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| author | Jonathan Wright <jonathan.wright@arm.com> | 2021-05-14 17:18:34 +0100 |
|---|---|---|
| committer | Jonathan Wright <jonathan.wright@arm.com> | 2021-05-19 14:44:39 +0100 |
| commit | ddbdb9a384f53419d0e6fbcca2a4534a2668e5f8 (patch) | |
| tree | 5d00891d47d407c5c7e88a8ea3e92c49a86e2ad1 /libcpp | |
| parent | 778ac63fe244b63380bd3b2dee4d20ff27332bce (diff) | |
| download | gcc-ddbdb9a384f53419d0e6fbcca2a4534a2668e5f8.zip gcc-ddbdb9a384f53419d0e6fbcca2a4534a2668e5f8.tar.gz gcc-ddbdb9a384f53419d0e6fbcca2a4534a2668e5f8.tar.bz2 | |
aarch64: Refactor aarch64_<sur>q<r>shr<u>n_n<mode> RTL pattern
Split the aarch64_<sur>q<r>shr<u>n_n<mode> pattern into separate
scalar and vector variants. Further split the vector pattern into
big/little endian variants that model the zero-high-half semantics
of the underlying instruction - allowing for more combinations with
the write-to-high-half variant (aarch64_<sur>q<r>shr<u>n2_n<mode>.)
gcc/ChangeLog:
2021-05-14 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Split builtin
generation for aarch64_<sur>q<r>shr<u>n_n<mode> pattern into
separate scalar and vector generators.
* config/aarch64/aarch64-simd.md
(aarch64_<sur>q<r>shr<u>n_n<mode>): Define as an expander and
split into...
(aarch64_<sur>q<r>shr<u>n_n<mode>_insn_le): This and...
(aarch64_<sur>q<r>shr<u>n_n<mode>_insn_be): This.
* config/aarch64/iterators.md: Define SD_HSDI iterator.
Diffstat (limited to 'libcpp')
0 files changed, 0 insertions, 0 deletions