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| author | Jonathan Wright <jonathan.wright@arm.com> | 2021-06-11 15:48:51 +0100 |
|---|---|---|
| committer | Jonathan Wright <jonathan.wright@arm.com> | 2021-06-16 14:21:52 +0100 |
| commit | d8a88cdae9c0c42ab7c5c65a5043c4f8bad349d2 (patch) | |
| tree | 43c2e4ceeabbc60b031b56d11965cecb77dbe074 /libcpp | |
| parent | ac6c858d072016ad2c409f1593fa290ad0d87e11 (diff) | |
| download | gcc-d8a88cdae9c0c42ab7c5c65a5043c4f8bad349d2.zip gcc-d8a88cdae9c0c42ab7c5c65a5043c4f8bad349d2.tar.gz gcc-d8a88cdae9c0c42ab7c5c65a5043c4f8bad349d2.tar.bz2 | |
aarch64: Model zero-high-half semantics of XTN instruction in RTL
Modeling the zero-high-half semantics of the XTN narrowing
instruction in RTL indicates to the compiler that this is a totally
destructive operation. This enables more RTL simplifications and also
prevents some register allocation issues.
Add new tests to narrow_zero_high_half.c to verify the benefit of
this change.
gcc/ChangeLog:
2021-06-11 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_xtn<mode>_insn_le):
Define - modeling zero-high-half semantics.
(aarch64_xtn<mode>): Change to an expander that emits the
appropriate instruction depending on endianness.
(aarch64_xtn<mode>_insn_be): Define - modeling zero-high-half
semantics.
(aarch64_xtn2<mode>_le): Rename to...
(aarch64_xtn2<mode>_insn_le): This.
(aarch64_xtn2<mode>_be): Rename to...
(aarch64_xtn2<mode>_insn_be): This.
(vec_pack_trunc_<mode>): Emit truncation instruction instead
of aarch64_xtn.
* config/aarch64/iterators.md (Vnarrowd): Add Vnarrowd mode
attribute iterator.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/narrow_zero_high_half.c: Add new tests.
Diffstat (limited to 'libcpp')
0 files changed, 0 insertions, 0 deletions