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| author | Uros Bizjak <ubizjak@gmail.com> | 2021-12-01 23:01:09 +0100 |
|---|---|---|
| committer | Uros Bizjak <ubizjak@gmail.com> | 2021-12-01 23:03:42 +0100 |
| commit | 7eb961d83b0eda53aeb1cfaacdc367e1952de613 (patch) | |
| tree | 21f566577f052fb2500939c1f09a4b95087aa8cf /libcpp | |
| parent | de3e5aae6c4b540e808c822c1e878b0a3304d09c (diff) | |
| download | gcc-7eb961d83b0eda53aeb1cfaacdc367e1952de613.zip gcc-7eb961d83b0eda53aeb1cfaacdc367e1952de613.tar.gz gcc-7eb961d83b0eda53aeb1cfaacdc367e1952de613.tar.bz2 | |
i386: Improve V8HI and V8HF inserts [PR102811]
Introduce vec_set_0 pattern for V8HI and V8HF modes to implement scalar
element 0 inserts to from a GP register, SSE register or memory. Also
add V8HI and V8HF AVX2 (x,x,x) alternative to PINSR insn pattern, which is
split after reload to a sequence of PBROADCASTW and PBLENDW.
The V8HF inserts from memory improve from:
- vpbroadcastw 4(%esp), %xmm1
- vpblendw $16, %xmm1, %xmm0, %xmm0
+ vpinsrw $4, 4(%esp), %xmm0, %xmm0
and V8HF inserts from SSE register to element 0 improve from:
vpxor %xmm2, %xmm2, %xmm2
- vpbroadcastw %xmm0, %xmm0
vpblendw $1, %xmm0, %xmm2, %xmm0
Based on the above improvements, the register allocator is able to determine
the optimal instruction (or instruction sequence) based on the register set
of the input value, so there is no need to manually expand V8HI and V8HF
inserts to the sequence of VEC_DUPLICATE and VEC_MERGE RTXes.
2021-12-01 Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/102811
* config/i386/sse.md (VI2F): Remove mode iterator.
(VI2F_256_512): New mode iterator.
(vec_set<V8_128:mode>_0): New insn pattern.
(vec_set<VI2F_256_512:mode>_0>): Rename from vec_set<VI2F:mode>mode.
Use VI2F_256_512 mode iterator instead of VI2F.
(*axv512fp16_movsh): Remove.
(<sse2p4_1>_pinsr<ssemodesuffix>): Add (x,x,x) AVX2 alternative.
Do not disable V8HF mode insn on AVX2 targets.
(pinsrw -> pbroadcast + pblendw peephole2): New peephole.
(pinsrw -> pbroadcast + pblendw splitter): New post-reload splitter.
* config/i386/i386.md (extendhfsf): Call gen_vec_setv8hf_0.
* config/i386/i386-expand.c (ix86_expand_vector_set)
<case E_V8HFmode>: Use vec_merge path for TARGET_AVX2.
gcc/testsuite/ChangeLog:
PR target/102881
* gcc.target/i386/pr102811-1.c: New test.
* gcc.target/i386/avx512fp16-1c.c (dg-final): Update
scan-assembler-times scan strings for ia32 targets.
* gcc.target/i386/pr102327-1.c (dg-final): Ditto.
* gcc.target/i386/pr102811.c: Rename from ...
* gcc.target/i386/avx512vl-vcvtps2ph-pr102811.c: ... this.
Diffstat (limited to 'libcpp')
0 files changed, 0 insertions, 0 deletions