aarch64: Fix up LDAPR codegen

Upon some further inspection I realised I had misunderstood some intricacies of the extending loads of the RCPC feature.
This patch fixes up the recent GCC support accordingly. In particular:
* The sign-extending forms are a form of LDAPURS* and are actually part of FEAT_RCPC2
that is enabled with Armv8.4-a rather than the base Armv8.3-a FEAT_RCPC.
The patch introduces a TARGET_RCPC2 macro and gates this combine pattern accordingly.
* The assembly output for the zero-extending LDAPR instruction should always use %w formatting for its destination register.

The testcase is split into zero-extending and sign-extending parts since they require different architecture pragmas.
It's also straightforward to add the rest of the FEAT_RCPC2 codegen
(with immediate offset addressing modes) but that can be done as a separate patch.
Apologies for not catching this sooner, but it hasn't been in trunk long, so no harm done.

Bootstrapped and tested on aarch64-none-linux-gnu.

gcc/ChangeLog:

	* config/aarch64/aarch64.h (TARGET_RCPC2): Define.
	* config/aarch64/atomics.md (*aarch64_atomic_load<ALLX:mode>_rcpc_zext):
	Adjust output template.
	(*aarch64_atomic_load<ALLX:mode>_rcpc_sex): Guard on TARGET_RCPC2.
	Adjust output template.
	* config/aarch64/iterators.md (w_sz): New mode attr.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/ldapr-ext.c: Rename to...
	* gcc.target/aarch64/ldapr-zext.c: ... This.  Fix expected assembly.
	* gcc.target/aarch64/ldapr-sext.c: New test.

0 files changed, 0 insertions, 0 deletions