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| author | demin.han <demin.han@starfivetech.com> | 2024-03-26 16:52:12 +0800 |
|---|---|---|
| committer | demin.han <demin.han@starfivetech.com> | 2024-04-29 19:18:56 +0800 |
| commit | ca2f531cc5db4f1020d4329976610356033e0246 (patch) | |
| tree | 8733fdade03cc44f004f2d57cb054ad7bdae7435 /libcpp | |
| parent | bca41a8d55e830c882b0f39246afead4fcfae6f7 (diff) | |
| download | gcc-ca2f531cc5db4f1020d4329976610356033e0246.zip gcc-ca2f531cc5db4f1020d4329976610356033e0246.tar.gz gcc-ca2f531cc5db4f1020d4329976610356033e0246.tar.bz2 | |
RISC-V: Refine the condition for add additional vars in RVV cost model
The adjacent_dr_p is sufficient and unnecessary condition for contiguous access.
So unnecessary live-ranges are added and result in smaller LMUL.
This patch uses MEMORY_ACCESS_TYPE as condition and constrains segment
load/store.
Tested on RV64 and no regression.
PR target/114506
gcc/ChangeLog:
* config/riscv/riscv-vector-costs.cc (non_contiguous_memory_access_p): Rename
(need_additional_vector_vars_p): Rename and refine condition
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/pr114506.c: New test.
Signed-off-by: demin.han <demin.han@starfivetech.com>
Diffstat (limited to 'libcpp')
0 files changed, 0 insertions, 0 deletions