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| author | Jin Ma <jinma@linux.alibaba.com> | 2023-06-19 13:02:47 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2023-06-19 13:02:47 -0600 |
| commit | dbcbc858c71f69da76d1f36d6bb5d72f2db11eda (patch) | |
| tree | 4a9629434541228a56360add55d3ee12dc2fa2de /libcpp | |
| parent | 827b2a279fc6ad5bb76e4d2c2eb3432955b5e11c (diff) | |
| download | gcc-dbcbc858c71f69da76d1f36d6bb5d72f2db11eda.zip gcc-dbcbc858c71f69da76d1f36d6bb5d72f2db11eda.tar.gz gcc-dbcbc858c71f69da76d1f36d6bb5d72f2db11eda.tar.bz2 | |
RISC-V: Save and restore FCSR in interrupt functions to avoid program errors.
In order to avoid interrupt functions to change the FCSR, it needs to be saved
and restored at the beginning and end of the function.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_compute_frame_info): Allocate frame for FCSR.
(riscv_for_each_saved_reg): Save and restore FCSR in interrupt functions.
* config/riscv/riscv.md (riscv_frcsr): New patterns.
(riscv_fscsr): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/interrupt-fcsr-1.c: New test.
* gcc.target/riscv/interrupt-fcsr-2.c: New test.
* gcc.target/riscv/interrupt-fcsr-3.c: New test.
Diffstat (limited to 'libcpp')
0 files changed, 0 insertions, 0 deletions