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| author | Hongyu Wang <hongyu.wang@intel.com> | 2023-08-17 08:30:04 +0800 |
|---|---|---|
| committer | Hongyu Wang <hongyu.wang@intel.com> | 2023-10-07 16:34:30 +0800 |
| commit | f49886484691d6ecec38ee83353ca34cc71410b7 (patch) | |
| tree | c1584930f0c57ff28e76bfa9f9c574c5191f82e6 /libcpp | |
| parent | ccdc0f0fcf6f240d5c4f059e6f38547a0cca9723 (diff) | |
| download | gcc-f49886484691d6ecec38ee83353ca34cc71410b7.zip gcc-f49886484691d6ecec38ee83353ca34cc71410b7.tar.gz gcc-f49886484691d6ecec38ee83353ca34cc71410b7.tar.bz2 | |
[APX EGPR] Handle GPR16 only vector move insns
For vector move insns like vmovdqa/vmovdqu, their evex counterparts
requrire explicit suffix 64/32/16/8. The usage of these instruction
are prohibited under AVX10_1 or AVX512F, so for we select
vmovaps/vmovups for vector load/store insns that contains EGPR if
ther is no AVX512VL, and keep the original move insn selection
otherwise.
gcc/ChangeLog:
* config/i386/i386.cc (ix86_get_ssemov): Check if egpr is used,
adjust mnemonic for vmovduq/vmovdqa.
* config/i386/sse.md (*<extract_type>_vinsert<shuffletype><extract_suf>_0):
Check if egpr is used, adjust mnemonic for vmovdqu/vmovdqa.
(avx_vec_concat<mode>): Likewise, and separate alternative 0 to
avx_noavx512f.
Co-authored-by: Kong Lingling <lingling.kong@intel.com>
Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
Diffstat (limited to 'libcpp')
0 files changed, 0 insertions, 0 deletions