[APX_EGPR] Handle legacy insns that only support GPR16 (4/5)

The APX enabled hardware should also be AVX10 enabled, thus for map2/3 insns
with evex counterpart, we assume auto promotion to EGPR under APX_F if the
insn uses GPR32. So for below insns, we disabled EGPR usage for their sse
mnenomics, while allowing egpr generation of their v prefixed mnemonics.

insn list:
1. pabsb/pabsw/pabsd
2. pextrb/pextrw/pextrd/pextrq
3. pinsrb/pinsrd/pinsrq
4. pshufb
5. extractps/insertps
6. pmaddubsw
7. pmulhrsw
8. packusdw
9. palignr
10. movntdqa
11. mpsadbw
12. pmuldq/pmulld
13. pmaxsb/pmaxsd, pminsb/pminsd
    pmaxud/pmaxuw, pminud/pminuw
14. (pmovsxbw/pmovsxbd/pmovsxbq,
     pmovsxwd/pmovsxwq, pmovsxdq
     pmovzxbw/pmovzxbd/pmovzxbq,
     pmovzxwd/pmovzxwq, pmovzxdq)
15. aesdec/aesdeclast, aesenc/aesenclast
16. pclmulqdq
17. gf2p8affineqb/gf2p8affineinvqb/gf2p8mulb

gcc/ChangeLog:

	* config/i386/i386.md (*movhi_internal): Split out non-gpr
	supported pextrw with mem constraint to avx/noavx alternatives,
	set jm and attr gpr32 0 to the noavx alternative.
	(*mov<mode>_internal): Likewise.
	* config/i386/mmx.md (mmx_pshufbv8qi3): Change "r/m/Bm" to
	"jr/jm/ja" and set_attr gpr32 0 for noavx alternative.
	(mmx_pshufbv4qi3): Likewise.
	(*mmx_pinsrd): Likewise.
	(*mmx_pinsrb): Likewise.
	(*pinsrb): Likewise.
	(mmx_pshufbv8qi3): Likewise.
	(mmx_pshufbv4qi3): Likewise.
	(@sse4_1_insertps_<mode>): Likewise.
	(*mmx_pextrw): Split altrenatives and map non-EGPR
	constraints, attr_gpr32 and attr_isa to noavx mnemonics.
	(*movv2qi_internal): Likewise.
	(*pextrw): Likewise.
	(*mmx_pextrb): Likewise.
	(*mmx_pextrb_zext): Likewise.
	(*pextrb): Likewise.
	(*pextrb_zext): Likewise.
	(vec_extractv2si_1): Likewise.
	(vec_extractv2si_1_zext): Likewise.
	* config/i386/sse.md: (vi128_h_r): New mode attr for
	pinsr{bw}/pextr{bw} with reg operand.
	(*abs<mode>2): Split altrenatives and %v in mnemonics, map
	non-EGPR constraints, gpr32 and isa attrs to noavx mnemonics.
	(*vec_extract<mode>): Likewise.
	(*vec_extract<mode>): Likewise for HFBF pattern.
	(*vec_extract<PEXTR_MODE12:mode>_zext): Likewise.
	(*vec_extractv4si_1): Likewise.
	(*vec_extractv4si_zext): Likewise.
	(*vec_extractv2di_1): Likewise.
	(*vec_concatv2si_sse4_1): Likewise.
	(<sse2p4_1>_pinsr<ssemodesuffix>): Likewise.
	(vec_concatv2di): Likewise.
	(*sse4_1_<code>v2qiv2di2<mask_name>_1): Likewise.
	(ssse3_avx2>_pshufb<mode>3<mask_name>): Change "r/m/Bm" to
	"jr/jm/ja" and set_attr gpr32 0 for noavx alternative, split
	%v for avx/noavx alternatives if necessary.
	(*vec_concatv2sf_sse4_1): Likewise.
	(*sse4_1_extractps): Likewise.
	(vec_set<mode>_0): Likewise for VI4F_128.
	(*vec_setv4sf_sse4_1): Likewise.
	(@sse4_1_insertps<mode>): Likewise.
	(ssse3_pmaddubsw128): Likewise.
	(*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>): Likewise.
	(<sse4_1_avx2>_packusdw<mask_name>): Likewise.
	(<ssse3_avx2>_palignr<mode>): Likewise.
	(<vi8_sse4_1_avx2_avx512>_movntdqa): Likewise.
	(<sse4_1_avx2>_mpsadbw): Likewise.
	(*sse4_1_mulv2siv2di3<mask_name>): Likewise.
	(*<sse4_1_avx2>_mul<mode>3<mask_name>): Likewise.
	(*sse4_1_<code><mode>3<mask_name>): Likewise.
	(*<code>v8hi3): Likewise.
	(*<code>v16qi3): Likewise.
	(*sse4_1_<code>v8qiv8hi2<mask_name>_1): Likewise.
	(*sse4_1_zero_extendv8qiv8hi2_3): Likewise.
	(*sse4_1_zero_extendv8qiv8hi2_4): Likewise.
	(*sse4_1_<code>v4qiv4si2<mask_name>_1): Likewise.
	(*sse4_1_<code>v4hiv4si2<mask_name>_1): Likewise.
	(*sse4_1_zero_extendv4hiv4si2_3): Likewise.
	(*sse4_1_zero_extendv4hiv4si2_4): Likewise.
	(*sse4_1_<code>v2hiv2di2<mask_name>_1): Likewise.
	(*sse4_1_<code>v2siv2di2<mask_name>_1): Likewise.
	(*sse4_1_zero_extendv2siv2di2_3): Likewise.
	(*sse4_1_zero_extendv2siv2di2_4): Likewise.
	(aesdec): Likewise.
	(aesdeclast): Likewise.
	(aesenc): Likewise.
	(aesenclast): Likewise.
	(pclmulqdq): Likewise.
	(vgf2p8affineinvqb_<mode><mask_name>): Likewise.
	(vgf2p8affineqb_<mode><mask_name>): Likewise.
	(vgf2p8mulb_<mode><mask_name>): Likewise.

Co-authored-by: Hongyu Wang <hongyu.wang@intel.com>
Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>

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