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| author | Monk Chiang <monk.chiang@sifive.com> | 2024-02-01 11:01:20 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2024-02-01 20:39:41 +0800 |
| commit | ec217f7282cd4284cecda1c65a1e04323e6c8354 (patch) | |
| tree | 7dcc9e840cb02e30d0392bcf54b9df3fa5ef22c3 /libcpp | |
| parent | 5c18df44fd1387653595869c9145c63fffb8cfac (diff) | |
| download | gcc-ec217f7282cd4284cecda1c65a1e04323e6c8354.zip gcc-ec217f7282cd4284cecda1c65a1e04323e6c8354.tar.gz gcc-ec217f7282cd4284cecda1c65a1e04323e6c8354.tar.bz2 | |
RISC-V: Support scheduling for sifive p600 series
Add sifive p600 series scheduler module. For more information
see https://www.sifive.com/cores/performance-p650-670.
Add sifive-p650, sifive-p670 for mcpu option will come in separate patches.
gcc/ChangeLog:
* config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
attribute, and include sifive-p600.md.
* config/riscv/generic-ooo.md: Update type attribute.
* config/riscv/generic.md: Update type attribute.
* config/riscv/sifive-7.md: Update type attribute.
* config/riscv/sifive-p600.md: New file.
* config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
Add sifive_p600.
* config/riscv/riscv.cc (sifive_p600_tune_info): New.
* config/riscv/riscv.h (TARGET_SFB_ALU): Update.
* doc/invoke.texi (RISC-V Options): Add sifive-p600-series
Diffstat (limited to 'libcpp')
0 files changed, 0 insertions, 0 deletions