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| author | Jonathan Wright <jonathan.wright@arm.com> | 2021-06-14 16:18:44 +0100 |
|---|---|---|
| committer | Jonathan Wright <jonathan.wright@arm.com> | 2021-06-16 14:22:42 +0100 |
| commit | dbfc149b639342a9555c60aa9ee787fb3d009316 (patch) | |
| tree | 2fddb90915757489cf18830e987f7a4a71352a8b /libcpp | |
| parent | d0889b5d37ff40149b44e3c7d82f693d430cd891 (diff) | |
| download | gcc-dbfc149b639342a9555c60aa9ee787fb3d009316.zip gcc-dbfc149b639342a9555c60aa9ee787fb3d009316.tar.gz gcc-dbfc149b639342a9555c60aa9ee787fb3d009316.tar.bz2 | |
aarch64: Model zero-high-half semantics of ADDHN/SUBHN instructions
Model the zero-high-half semantics of the narrowing arithmetic Neon
instructions in the aarch64_<sur><addsub>hn<mode> RTL pattern.
Modeling these semantics allows for better RTL combinations while
also removing some register allocation issues as the compiler now
knows that the operation is totally destructive.
Add new tests to narrow_zero_high_half.c to verify the benefit of
this change.
gcc/ChangeLog:
2021-06-14 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn<mode>):
Change to an expander that emits the correct instruction
depending on endianness.
(aarch64_<sur><addsub>hn<mode>_insn_le): Define.
(aarch64_<sur><addsub>hn<mode>_insn_be): Define.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/narrow_zero_high_half.c: Add new tests.
Diffstat (limited to 'libcpp')
0 files changed, 0 insertions, 0 deletions