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| author | Edwin Lu <ewlu@rivosinc.com> | 2024-02-14 12:06:38 -0800 |
|---|---|---|
| committer | Edwin Lu <ewlu@rivosinc.com> | 2024-02-21 11:54:37 -0800 |
| commit | bc6b42666cfe1467774b942c7afabe480e3b5ccb (patch) | |
| tree | a6bb94850c9d7c19c7a67a8803d0c23ed04cd191 /libcpp | |
| parent | 67a29f99cc81384b9245ac5997e47bcf3ff84545 (diff) | |
| download | gcc-bc6b42666cfe1467774b942c7afabe480e3b5ccb.zip gcc-bc6b42666cfe1467774b942c7afabe480e3b5ccb.tar.gz gcc-bc6b42666cfe1467774b942c7afabe480e3b5ccb.tar.bz2 | |
RISC-V: Quick and simple fixes to testcases that break due to reordering
The following test cases are easily fixed with small updates to the expected
assembly order. Additionally make calling-convention testcases more robust
PR target/113249
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c:
Rearrange and adjust asm-checker times
* gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Ditto
* gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Ditto
* gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Ditto
* gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Ditto
* gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Ditto
* gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-12.c:
Rearrange assembly
* gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: Ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: Ditto
* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: Ditto
* gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Change expected vsetvl
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Diffstat (limited to 'libcpp')
0 files changed, 0 insertions, 0 deletions