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| author | Tamar Christina <tamar.christina@arm.com> | 2024-02-22 15:32:08 +0000 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2024-02-22 15:32:08 +0000 |
| commit | 7d8585c0c0e5934780281abdee256ae6553e56e8 (patch) | |
| tree | e1df7e789c562709cf4a8c3f6bad8a668475c068 /libcpp | |
| parent | c1667b1ef538e4da10cf83bdf1ae62d7bdd96128 (diff) | |
| download | gcc-7d8585c0c0e5934780281abdee256ae6553e56e8.zip gcc-7d8585c0c0e5934780281abdee256ae6553e56e8.tar.gz gcc-7d8585c0c0e5934780281abdee256ae6553e56e8.tar.bz2 | |
AArch64: update vget_set_lane_1.c test output
In the vget_set_lane_1.c test the following entries now generate a zip1 instead of an INS
BUILD_TEST (float32x2_t, float32x2_t, , , f32, 1, 0)
BUILD_TEST (int32x2_t, int32x2_t, , , s32, 1, 0)
BUILD_TEST (uint32x2_t, uint32x2_t, , , u32, 1, 0)
This is because the non-Q variant for indices 0 and 1 are just shuffling values.
There is no perf difference between INS SIMD to SIMD and ZIP on Arm uArches but
preferring the INS alternative has a drawback on all uArches as ZIP being a three
operand instruction can be used to tie the result to the return register whereas
INS would require an fmov.
As such just update the test file for now.
gcc/testsuite/ChangeLog:
PR target/112375
* gcc.target/aarch64/vget_set_lane_1.c: Update test output.
Diffstat (limited to 'libcpp')
0 files changed, 0 insertions, 0 deletions