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| author | Richard Earnshaw <rearnsha@arm.com> | 2017-07-05 15:32:47 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2017-07-05 15:32:47 +0000 |
| commit | 75e2d19bc75321122cbe87bc57a5d825dd2fc6df (patch) | |
| tree | 3dcc7b5ab4cd84f2be1827f4f5bed72e9822c389 /libcpp | |
| parent | d8448c583ef6ce71f2ee46749ee24d0218df6907 (diff) | |
| download | gcc-75e2d19bc75321122cbe87bc57a5d825dd2fc6df.zip gcc-75e2d19bc75321122cbe87bc57a5d825dd2fc6df.tar.gz gcc-75e2d19bc75321122cbe87bc57a5d825dd2fc6df.tar.bz2 | |
[ARM] Implement TARGET_FIXED_CONDITION_CODE_REGS
This patch implements TARGET_FIXED_CONDITION_CODE_REGS on ARM.
We have two main cases to consider: in Thumb1 code there are no
condition code registers, so we simply return false. For other
cases we set the the first pointer to CC_REGNUM and the second to
VFPCC_REGNUM iff generating hard-float code.
Running the CSiBE benchmark I see a couple of cases (both in the same
file) where this feature kicks in, so it's not a major change.
* config/arm/arm.c (arm_fixed_condition_code_regs): New function.
(TARGET_FIXED_CONDITION_CODE_REGS): Redefine.
From-SVN: r250005
Diffstat (limited to 'libcpp')
0 files changed, 0 insertions, 0 deletions