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| author | Tamar Christina <tamar.christina@arm.com> | 2023-11-09 14:18:48 +0000 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2023-11-09 14:18:48 +0000 |
| commit | ffd40d3b233d63c925cceb0dcd5a4fc8925e2993 (patch) | |
| tree | 088f078423d37c250942e86a5b42521394710f56 /libcpp/line-map.cc | |
| parent | 830460d67a10549939602ba323ea3fa65fb7de20 (diff) | |
| download | gcc-ffd40d3b233d63c925cceb0dcd5a4fc8925e2993.zip gcc-ffd40d3b233d63c925cceb0dcd5a4fc8925e2993.tar.gz gcc-ffd40d3b233d63c925cceb0dcd5a4fc8925e2993.tar.bz2 | |
AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD inefficient [PR109154]
SVE has much bigger immediate encoding range for bitmasks than Advanced SIMD has
and so on a system that is SVE capable if we need an Advanced SIMD Inclusive-OR
by immediate and would require a reload then use an unpredicated SVE ORR instead.
This has both speed and size improvements.
gcc/ChangeLog:
PR tree-optimization/109154
* config/aarch64/aarch64.md (<optab><mode>3): Add SVE split case.
* config/aarch64/aarch64-simd.md (ior<mode>3<vczle><vczbe>): Likewise.
* config/aarch64/predicates.md(aarch64_orr_imm_sve_advsimd): New.
gcc/testsuite/ChangeLog:
PR tree-optimization/109154
* gcc.target/aarch64/sve/fneg-abs_1.c: Updated.
* gcc.target/aarch64/sve/fneg-abs_2.c: Updated.
* gcc.target/aarch64/sve/fneg-abs_4.c: Updated.
Diffstat (limited to 'libcpp/line-map.cc')
0 files changed, 0 insertions, 0 deletions