RISC-V: Bugfix for merging undefined tmp register in math

For math function autovec, there will be one step like

rtx tmp = gen_reg_rtx (vec_int_mode);
emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode);

The MU will leave the tmp (aka dest register) register unmasked elements
unchanged and it is undefined here. This patch would like to adjust the
MU to MA.

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (enum insn_type): Add new type
	values.
	* config/riscv/riscv-v.cc (emit_vec_cvt_x_f): Add undef merge
	operand handling.
	(expand_vec_ceil): Take MA instead of MU for tmp register.
	(expand_vec_floor): Ditto.
	(expand_vec_nearbyint): Ditto.
	(expand_vec_rint): Ditto.
	(expand_vec_round): Ditto.
	(expand_vec_roundeven): Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions