aarch64: Fix +nosimd handling of FPR moves

8-bit and 16-bit FPR moves would ICE for +nosimd+fp, and some other
moves would handle FPR<-zero inefficiently.  This is very much a
niche case at the moment, but something like it becomes more
important with SME streaming mode.

The si, di and vector tests already passed, they're just included for
completeness.

We're a bit inconsistent about whether alternatives involving FPRs
are marked with arch==fp or arch=* (i.e. default).  E.g. FPR loads
and stores are sometimes * and sometimes fp.

IMO * makes more sense.  FPRs should not be used at all without
TARGET_FLOAT, so TARGET_FLOAT represents the base architecture
when FPRs are enabled.  I think it's more useful if non-default
arches represent a genuine restriction.

gcc/
	* config/aarch64/aarch64.md (*mov<SHORT:mode>_aarch64): Extend
	w<-w, r<-w and w<-r alternatives to !simd, using 32-bit moves
	in that case.  Extend w<-r to w<-Z.
	(*mov<HFBF:mode>_aarch64): Likewise, but with Y instead of Z.
	(*movti_aarch64): Use an FMOV from XZR for w<-Z if MOVI is not
	available.
	(define_split): Do not apply the floating-point immediate-to-register
	split to zeros, even if MOVI is not available.

gcc/testsuite/
	* gcc.target/aarch64/movqi_1.c: New test.
	* gcc.target/aarch64/movhi_1.c: Likewise.
	* gcc.target/aarch64/movsi_1.c: Likewise.
	* gcc.target/aarch64/movdi_2.c: Likewise.
	* gcc.target/aarch64/movti_2.c: Likewise.
	* gcc.target/aarch64/movhf_1.c: Likewise.
	* gcc.target/aarch64/movsf_1.c: Likewise.
	* gcc.target/aarch64/movdf_1.c: Likewise.
	* gcc.target/aarch64/movtf_2.c: Likewise.
	* gcc.target/aarch64/movv8qi_1.c: Likewise.
	* gcc.target/aarch64/movv16qi_1.c: Likewise.

0 files changed, 0 insertions, 0 deletions