[RISCV] Fix PR 106586: riscv32 vs ZBS

The problem here is two fold. With RISCV32, 32bit
const_int are always signed extended to 64bit in HWI.
So that means for SINGLE_BIT_MASK_OPERAND, it should
mask off the upper bits to see it is a single bit
for !TARGET_64BIT.
Plus there are a few locations which forget to call
trunc_int_for_mode when generating a SImode constant
so they are not sign extended correctly for HWI.
The predicates single_bit_mask_operand and
not_single_bit_mask_operand need get the same handling
as SINGLE_BIT_MASK_OPERAND so just use SINGLE_BIT_MASK_OPERAND.

OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with
--with-arch=rvNimafdc_zba_zbb_zbc_zbs where N is replaced with 32 or 64.

Thanks,
Andrew Pinski

gcc/ChangeLog:

	PR target/106586
	* config/riscv/predicates.md (single_bit_mask_operand):
	Use SINGLE_BIT_MASK_OPERAND instead of directly calling pow2p_hwi.
	(not_single_bit_mask_operand): Likewise.
	* config/riscv/riscv.cc (riscv_build_integer_1): Don't special case
	1<<31 for 32bits as it is already handled.
	Call trunc_int_for_mode on the upper part after the subtraction.
	(riscv_move_integer): Call trunc_int_for_mode before generating
	the integer just make sure the constant has been sign extended
	corectly.
	(riscv_emit_int_compare): Call trunc_int_for_mode after doing the
	addition for the new rhs.
	* config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): If !TARGET64BIT,
	then mask off the upper 32bits of the HWI as it will be sign extended.

0 files changed, 0 insertions, 0 deletions