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| author | David Candler <David.Candler@arm.com> | 2020-11-06 17:53:03 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2020-11-06 17:53:03 +0000 |
| commit | 05f1883cfd041adba5f595e97118100b6e00a524 (patch) | |
| tree | be113c28a40d6f8ee01b2412f99f04acd4f99704 /libcc1 | |
| parent | 4b5f564a5d958295d51a1a7ff825896a89f22b75 (diff) | |
| download | gcc-05f1883cfd041adba5f595e97118100b6e00a524.zip gcc-05f1883cfd041adba5f595e97118100b6e00a524.tar.gz gcc-05f1883cfd041adba5f595e97118100b6e00a524.tar.bz2 | |
aarch64: Use intrinsics for upper saturating shift right
The use of vqshrn_high_n_s32 was triggering an unneeded register move, because
sqshrn2 is destructive but was declared as inline assembly in arm_neon.h. This
patch implements sqshrn2 and uqshrn2 as actual intrinsics which do not trigger
the unnecessary move, along with new tests to cover them.
gcc/ChangeLog
2020-11-06 David Candler <david.candler@arm.com>
* config/aarch64/aarch64-builtins.c
(TYPES_SHIFT2IMM): Add define.
(TYPES_SHIFT2IMM_UUSS): Add define.
(TYPES_USHIFT2IMM): Add define.
* config/aarch64/aarch64-simd.md
(aarch64_<sur>q<r>shr<u>n2_n<mode>): Add new insn for upper saturating shift right.
* config/aarch64/aarch64-simd-builtins.def: Add intrinsics.
* config/aarch64/arm_neon.h:
(vqrshrn_high_n_s16): Expand using intrinsic rather than inline asm.
(vqrshrn_high_n_s32): Likewise.
(vqrshrn_high_n_s64): Likewise.
(vqrshrn_high_n_u16): Likewise.
(vqrshrn_high_n_u32): Likewise.
(vqrshrn_high_n_u64): Likewise.
(vqrshrun_high_n_s16): Likewise.
(vqrshrun_high_n_s32): Likewise.
(vqrshrun_high_n_s64): Likewise.
(vqshrn_high_n_s16): Likewise.
(vqshrn_high_n_s32): Likewise.
(vqshrn_high_n_s64): Likewise.
(vqshrn_high_n_u16): Likewise.
(vqshrn_high_n_u32): Likewise.
(vqshrn_high_n_u64): Likewise.
(vqshrun_high_n_s16): Likewise.
(vqshrun_high_n_s32): Likewise.
(vqshrun_high_n_s64): Likewise.
gcc/testsuite/ChangeLog
2020-11-06 David Candler <david.candler@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vqrshrn_high_n.c: New testcase.
* gcc.target/aarch64/advsimd-intrinsics/vqrshrun_high_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vqshrn_high_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vqshrun_high_n.c: Likewise.
* gcc.target/aarch64/narrow_high-intrinsics.c: Update expected assembler
for sqshrun2, sqrshrun2, sqshrn2, uqshrn2, sqrshrn2 and uqrshrn2.
Diffstat (limited to 'libcc1')
0 files changed, 0 insertions, 0 deletions