RISC-V: Add RVV FMA auto-vectorization support

This patch support FMA auto-vectorization pattern. Let's RA decide
vmacc or vmadd.

Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

	* config/riscv/autovec.md (fma<mode>4): New pattern.
	(*fma<mode>): Ditto.
	* config/riscv/riscv-protos.h (enum insn_type): New enum.
	(emit_vlmax_ternary_insn): New function.
	* config/riscv/riscv-v.cc (emit_vlmax_ternary_insn): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/rvv.exp: Add ternary tests
	* gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-3.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: New test.

10 files changed, 476 insertions, 0 deletions

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index b24867a..0314e75 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -518,3 +518,68 @@
 					   riscv_vector::RVV_UNOP_MU, ops);
   DONE;
 })
+
+;; =========================================================================
+;; == Ternary arithmetic
+;; =========================================================================
+
+;; -------------------------------------------------------------------------
+;; ---- [INT] VMACC and VMADD
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vmacc
+;; - vmadd
+;; -------------------------------------------------------------------------
+
+;; We can't expand FMA for the following reasons:
+;; 1. Before RA, we don't know which multiply-add instruction is the ideal one.
+;;    The vmacc is the ideal instruction when operands[3] overlaps operands[0].
+;;    The vmadd is the ideal instruction when operands[1|2] overlaps operands[0].
+;; 2. According to vector.md, the multiply-add patterns has 'merge' operand which
+;;    is the operands[5]. Since operands[5] should overlap operands[0], this operand
+;;    should be allocated the same regno as operands[1|2|3].
+;; 3. The 'merge' operand is always a real merge operand and we don't allow undefined
+;;    operand.
+;; 4. The operation of FMA pattern needs VLMAX vsetlvi which needs a VL operand.
+;;
+;; In this situation, we design the codegen of FMA as follows:
+;; 1. clobber a scratch in the expand pattern of FMA.
+;; 2. Let's RA decide which input operand (operands[1|2|3]) overlap operands[0].
+;; 3. Generate instructions (vmacc or vmadd) according to the register allocation
+;;    result after reload_completed.
+(define_expand "fma<mode>4"
+  [(parallel
+    [(set (match_operand:VI 0 "register_operand"     "=vr")
+	  (plus:VI
+	    (mult:VI
+	      (match_operand:VI 1 "register_operand" " vr")
+	      (match_operand:VI 2 "register_operand" " vr"))
+	    (match_operand:VI 3 "register_operand"   " vr")))
+     (clobber (match_scratch:SI 4))])]
+  "TARGET_VECTOR"
+  {})
+
+(define_insn_and_split "*fma<mode>"
+  [(set (match_operand:VI 0 "register_operand"     "=vr, vr, ?&vr")
+	(plus:VI
+	  (mult:VI
+	    (match_operand:VI 1 "register_operand" " %0, vr,   vr")
+	    (match_operand:VI 2 "register_operand" " vr, vr,   vr"))
+	  (match_operand:VI 3 "register_operand"   " vr,  0,   vr")))
+   (clobber (match_scratch:SI 4 "=r,r,r"))]
+  "TARGET_VECTOR"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+  {
+    PUT_MODE (operands[4], Pmode);
+    riscv_vector::emit_vlmax_vsetvl (<MODE>mode, operands[4]);
+    if (which_alternative == 2)
+      emit_insn (gen_rtx_SET (operands[0], operands[3]));
+    rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]};
+    riscv_vector::emit_vlmax_ternary_insn (code_for_pred_mul_plus (<MODE>mode),
+					  riscv_vector::RVV_TERNOP, ops, operands[4]);
+    DONE;
+  }
+  [(set_attr "type" "vimuladd")
+   (set_attr "mode" "<MODE>")])
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index c031354..0462f96 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -141,6 +141,7 @@ enum insn_type
   RVV_CMP_OP = 4,
   RVV_CMP_MU_OP = RVV_CMP_OP + 2, /* +2 means mask and maskoff operand.  */
   RVV_UNOP_MU = RVV_UNOP + 2,	  /* Likewise.  */
+  RVV_TERNOP = 5,
 };
 enum vlmul_type
 {
@@ -177,6 +178,7 @@ bool legitimize_move (rtx, rtx);
 void emit_vlmax_vsetvl (machine_mode, rtx);
 void emit_hard_vlmax_vsetvl (machine_mode, rtx);
 void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);
+void emit_vlmax_ternary_insn (unsigned, int, rtx *, rtx = 0);
 void emit_nonvlmax_insn (unsigned, int, rtx *, rtx);
 void emit_vlmax_merge_insn (unsigned, int, rtx *);
 void emit_vlmax_cmp_insn (unsigned, rtx *);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 6928c8d2..a5715bb 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -362,6 +362,26 @@ emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, rtx vl)
   e.emit_insn ((enum insn_code) icode, ops);
 }
 
+/* This function emits a {VLMAX, TAIL_ANY, MASK_ANY} vsetvli followed by the
+ * ternary operation which always has a real merge operand.  */
+void
+emit_vlmax_ternary_insn (unsigned icode, int op_num, rtx *ops, rtx vl)
+{
+  machine_mode dest_mode = GET_MODE (ops[0]);
+  machine_mode mask_mode = get_mask_mode (dest_mode).require ();
+  /* We have a maximum of 11 operands for RVV instruction patterns according to
+   * vector.md.  */
+  insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true,
+		       /*FULLY_UNMASKED_P*/ true,
+		       /*USE_REAL_MERGE_P*/ true, /*HAS_AVL_P*/ true,
+		       /*VLMAX_P*/ true,
+		       /*DEST_MODE*/ dest_mode, /*MASK_MODE*/ mask_mode);
+  e.set_policy (TAIL_ANY);
+  e.set_policy (MASK_ANY);
+  e.set_vl (vl);
+  e.emit_insn ((enum insn_code) icode, ops);
+}
+
 /* This function emits a {NONVLMAX, TAIL_ANY, MASK_ANY} vsetvli followed by the
  * actual operation.  */
 void
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c
new file mode 100644
index 0000000..1996ca6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE)                                                        \
+  __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dst,            \
+					      TYPE *__restrict a,              \
+					      TYPE *__restrict b, int n)       \
+  {                                                                            \
+    for (int i = 0; i < n; i++)                                                \
+      dst[i] += a[i] * b[i];                                                   \
+  }
+
+#define TEST_ALL()                                                             \
+  TEST_TYPE (int8_t)                                                           \
+  TEST_TYPE (uint8_t)                                                          \
+  TEST_TYPE (int16_t)                                                          \
+  TEST_TYPE (uint16_t)                                                         \
+  TEST_TYPE (int32_t)                                                          \
+  TEST_TYPE (uint32_t)                                                         \
+  TEST_TYPE (int64_t)                                                          \
+  TEST_TYPE (uint64_t)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvmadd\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvmv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c
new file mode 100644
index 0000000..89eeaf6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE)                                                        \
+  __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dest1,          \
+					      TYPE *__restrict dest2,          \
+					      TYPE *__restrict dest3,          \
+					      TYPE *__restrict src1,           \
+					      TYPE *__restrict src2, int n)    \
+  {                                                                            \
+    for (int i = 0; i < n; ++i)                                                \
+      {                                                                        \
+	dest1[i] += src1[i] * src2[i];                                         \
+	dest2[i] += src1[i] * dest1[i];                                        \
+	dest3[i] += src2[i] * dest2[i];                                        \
+      }                                                                        \
+  }
+
+#define TEST_ALL()                                                             \
+  TEST_TYPE (int8_t)                                                           \
+  TEST_TYPE (uint8_t)                                                          \
+  TEST_TYPE (int16_t)                                                          \
+  TEST_TYPE (uint16_t)                                                         \
+  TEST_TYPE (int32_t)                                                          \
+  TEST_TYPE (uint32_t)                                                         \
+  TEST_TYPE (int64_t)                                                          \
+  TEST_TYPE (uint64_t)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvmacc\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvmv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c
new file mode 100644
index 0000000..127e701
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE)                                                        \
+  __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dest1,          \
+					      TYPE *__restrict dest2,          \
+					      TYPE *__restrict dest3,          \
+					      TYPE *__restrict src1,           \
+					      TYPE *__restrict src2, int n)    \
+  {                                                                            \
+    for (int i = 0; i < n; ++i)                                                \
+      {                                                                        \
+	dest1[i] = src1[i] * src2[i] + dest2[i];                               \
+	dest2[i] += src1[i] * dest1[i];                                        \
+	dest3[i] += src2[i] * dest2[i];                                        \
+      }                                                                        \
+  }
+
+#define TEST_ALL()                                                             \
+  TEST_TYPE (int8_t)                                                           \
+  TEST_TYPE (uint8_t)                                                          \
+  TEST_TYPE (int16_t)                                                          \
+  TEST_TYPE (uint16_t)                                                         \
+  TEST_TYPE (int32_t)                                                          \
+  TEST_TYPE (uint32_t)                                                         \
+  TEST_TYPE (int64_t)                                                          \
+  TEST_TYPE (uint64_t)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvmv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c
new file mode 100644
index 0000000..1f69b69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c
@@ -0,0 +1,84 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop-1.c"
+
+#define TEST_LOOP(TYPE, NUM)                                                   \
+  {                                                                            \
+    TYPE array1_##NUM[NUM] = {};                                               \
+    TYPE array2_##NUM[NUM] = {};                                               \
+    TYPE array3_##NUM[NUM] = {};                                               \
+    TYPE array4_##NUM[NUM] = {};                                               \
+    for (int i = 0; i < NUM; ++i)                                              \
+      {                                                                        \
+	array1_##NUM[i] = (i & 1) + 5;                                         \
+	array2_##NUM[i] = i - NUM / 3;                                         \
+	array3_##NUM[i] = NUM - NUM / 3 - i;                                   \
+	array4_##NUM[i] = NUM - NUM / 3 - i;                                   \
+	asm volatile("" ::: "memory");                                         \
+      }                                                                        \
+    ternop_##TYPE (array3_##NUM, array1_##NUM, array2_##NUM, NUM);             \
+    for (int i = 0; i < NUM; i++)                                              \
+      if (array3_##NUM[i]                                                      \
+	  != (TYPE) (array1_##NUM[i] * array2_##NUM[i] + array4_##NUM[i]))     \
+	__builtin_abort ();                                                    \
+  }
+
+int __attribute__ ((optimize (0))) main ()
+{
+  TEST_LOOP (int8_t, 7)
+  TEST_LOOP (uint8_t, 7)
+  TEST_LOOP (int16_t, 7)
+  TEST_LOOP (uint16_t, 7)
+  TEST_LOOP (int32_t, 7)
+  TEST_LOOP (uint32_t, 7)
+  TEST_LOOP (int64_t, 7)
+  TEST_LOOP (uint64_t, 7)
+
+  TEST_LOOP (int8_t, 16)
+  TEST_LOOP (uint8_t, 16)
+  TEST_LOOP (int16_t, 16)
+  TEST_LOOP (uint16_t, 16)
+  TEST_LOOP (int32_t, 16)
+  TEST_LOOP (uint32_t, 16)
+  TEST_LOOP (int64_t, 16)
+  TEST_LOOP (uint64_t, 16)
+
+  TEST_LOOP (int8_t, 77)
+  TEST_LOOP (uint8_t, 77)
+  TEST_LOOP (int16_t, 77)
+  TEST_LOOP (uint16_t, 77)
+  TEST_LOOP (int32_t, 77)
+  TEST_LOOP (uint32_t, 77)
+  TEST_LOOP (int64_t, 77)
+  TEST_LOOP (uint64_t, 77)
+  
+  TEST_LOOP (int8_t, 128)
+  TEST_LOOP (uint8_t, 128)
+  TEST_LOOP (int16_t, 128)
+  TEST_LOOP (uint16_t, 128)
+  TEST_LOOP (int32_t, 128)
+  TEST_LOOP (uint32_t, 128)
+  TEST_LOOP (int64_t, 128)
+  TEST_LOOP (uint64_t, 128)
+
+  TEST_LOOP (int8_t, 15641)
+  TEST_LOOP (uint8_t, 15641)
+  TEST_LOOP (int16_t, 15641)
+  TEST_LOOP (uint16_t, 15641)
+  TEST_LOOP (int32_t, 15641)
+  TEST_LOOP (uint32_t, 15641)
+  TEST_LOOP (int64_t, 15641)
+  TEST_LOOP (uint64_t, 15641)
+  
+  TEST_LOOP (int8_t, 795)
+  TEST_LOOP (uint8_t, 795)
+  TEST_LOOP (int16_t, 795)
+  TEST_LOOP (uint16_t, 795)
+  TEST_LOOP (int32_t, 795)
+  TEST_LOOP (uint32_t, 795)
+  TEST_LOOP (int64_t, 795)
+  TEST_LOOP (uint64_t, 795)
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c
new file mode 100644
index 0000000..103b98a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c
@@ -0,0 +1,104 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop-2.c"
+
+#define TEST_LOOP(TYPE, NUM)                                                   \
+  {                                                                            \
+    TYPE array1_##NUM[NUM] = {};                                               \
+    TYPE array2_##NUM[NUM] = {};                                               \
+    TYPE array3_##NUM[NUM] = {};                                               \
+    TYPE array4_##NUM[NUM] = {};                                               \
+    TYPE array5_##NUM[NUM] = {};                                               \
+    TYPE array6_##NUM[NUM] = {};                                               \
+    TYPE array7_##NUM[NUM] = {};                                               \
+    TYPE array8_##NUM[NUM] = {};                                               \
+    for (int i = 0; i < NUM; ++i)                                              \
+      {                                                                        \
+	array1_##NUM[i] = (i & 1) + 5;                                         \
+	array2_##NUM[i] = i - NUM / 3;                                         \
+	array3_##NUM[i] = NUM - NUM / 3 - i;                                   \
+	array6_##NUM[i] = NUM - NUM / 3 - i;                                   \
+	array4_##NUM[i] = NUM - NUM / 2 + i;                                   \
+	array7_##NUM[i] = NUM - NUM / 2 + i;                                   \
+	array5_##NUM[i] = NUM + i * 7;                                         \
+	array8_##NUM[i] = NUM + i * 7;                                         \
+	asm volatile("" ::: "memory");                                         \
+      }                                                                        \
+    ternop_##TYPE (array3_##NUM, array4_##NUM, array5_##NUM, array1_##NUM,     \
+		   array2_##NUM, NUM);                                         \
+    for (int i = 0; i < NUM; i++)                                              \
+      {                                                                        \
+	array6_##NUM[i]                                                        \
+	  = (TYPE) (array1_##NUM[i] * array2_##NUM[i] + array6_##NUM[i]);      \
+	if (array3_##NUM[i] != array6_##NUM[i])                                \
+	  __builtin_abort ();                                                  \
+	array7_##NUM[i]                                                        \
+	  = (TYPE) (array1_##NUM[i] * array6_##NUM[i] + array7_##NUM[i]);      \
+	if (array4_##NUM[i] != array7_##NUM[i])                                \
+	  __builtin_abort ();                                                  \
+	array8_##NUM[i]                                                        \
+	  = (TYPE) (array2_##NUM[i] * array7_##NUM[i] + array8_##NUM[i]);      \
+	if (array5_##NUM[i] != array8_##NUM[i])                                \
+	  __builtin_abort ();                                                  \
+      }                                                                        \
+  }
+
+int __attribute__ ((optimize (0))) main ()
+{
+  TEST_LOOP (int8_t, 7)
+  TEST_LOOP (uint8_t, 7)
+  TEST_LOOP (int16_t, 7)
+  TEST_LOOP (uint16_t, 7)
+  TEST_LOOP (int32_t, 7)
+  TEST_LOOP (uint32_t, 7)
+  TEST_LOOP (int64_t, 7)
+  TEST_LOOP (uint64_t, 7)
+
+  TEST_LOOP (int8_t, 16)
+  TEST_LOOP (uint8_t, 16)
+  TEST_LOOP (int16_t, 16)
+  TEST_LOOP (uint16_t, 16)
+  TEST_LOOP (int32_t, 16)
+  TEST_LOOP (uint32_t, 16)
+  TEST_LOOP (int64_t, 16)
+  TEST_LOOP (uint64_t, 16)
+
+  TEST_LOOP (int8_t, 77)
+  TEST_LOOP (uint8_t, 77)
+  TEST_LOOP (int16_t, 77)
+  TEST_LOOP (uint16_t, 77)
+  TEST_LOOP (int32_t, 77)
+  TEST_LOOP (uint32_t, 77)
+  TEST_LOOP (int64_t, 77)
+  TEST_LOOP (uint64_t, 77)
+
+  TEST_LOOP (int8_t, 128)
+  TEST_LOOP (uint8_t, 128)
+  TEST_LOOP (int16_t, 128)
+  TEST_LOOP (uint16_t, 128)
+  TEST_LOOP (int32_t, 128)
+  TEST_LOOP (uint32_t, 128)
+  TEST_LOOP (int64_t, 128)
+  TEST_LOOP (uint64_t, 128)
+
+  TEST_LOOP (int8_t, 15641)
+  TEST_LOOP (uint8_t, 15641)
+  TEST_LOOP (int16_t, 15641)
+  TEST_LOOP (uint16_t, 15641)
+  TEST_LOOP (int32_t, 15641)
+  TEST_LOOP (uint32_t, 15641)
+  TEST_LOOP (int64_t, 15641)
+  TEST_LOOP (uint64_t, 15641)
+
+  TEST_LOOP (int8_t, 795)
+  TEST_LOOP (uint8_t, 795)
+  TEST_LOOP (int16_t, 795)
+  TEST_LOOP (uint16_t, 795)
+  TEST_LOOP (int32_t, 795)
+  TEST_LOOP (uint32_t, 795)
+  TEST_LOOP (int64_t, 795)
+  TEST_LOOP (uint64_t, 795)
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c
new file mode 100644
index 0000000..eac5408
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c
@@ -0,0 +1,104 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include "ternop-3.c"
+
+#define TEST_LOOP(TYPE, NUM)                                                   \
+  {                                                                            \
+    TYPE array1_##NUM[NUM] = {};                                               \
+    TYPE array2_##NUM[NUM] = {};                                               \
+    TYPE array3_##NUM[NUM] = {};                                               \
+    TYPE array4_##NUM[NUM] = {};                                               \
+    TYPE array5_##NUM[NUM] = {};                                               \
+    TYPE array6_##NUM[NUM] = {};                                               \
+    TYPE array7_##NUM[NUM] = {};                                               \
+    TYPE array8_##NUM[NUM] = {};                                               \
+    for (int i = 0; i < NUM; ++i)                                              \
+      {                                                                        \
+	array1_##NUM[i] = (i & 1) + 5;                                         \
+	array2_##NUM[i] = i - NUM / 3;                                         \
+	array3_##NUM[i] = NUM - NUM / 3 - i;                                   \
+	array6_##NUM[i] = NUM - NUM / 3 - i;                                   \
+	array4_##NUM[i] = NUM - NUM / 2 + i;                                   \
+	array7_##NUM[i] = NUM - NUM / 2 + i;                                   \
+	array5_##NUM[i] = NUM + i * 7;                                         \
+	array8_##NUM[i] = NUM + i * 7;                                         \
+	asm volatile("" ::: "memory");                                         \
+      }                                                                        \
+    ternop_##TYPE (array3_##NUM, array4_##NUM, array5_##NUM, array1_##NUM,     \
+		   array2_##NUM, NUM);                                         \
+    for (int i = 0; i < NUM; i++)                                              \
+      {                                                                        \
+	array6_##NUM[i]                                                        \
+	  = (TYPE) (array1_##NUM[i] * array2_##NUM[i] + array7_##NUM[i]);      \
+	if (array3_##NUM[i] != array6_##NUM[i])                                \
+	  __builtin_abort ();                                                  \
+	array7_##NUM[i]                                                        \
+	  = (TYPE) (array1_##NUM[i] * array6_##NUM[i] + array7_##NUM[i]);      \
+	if (array4_##NUM[i] != array7_##NUM[i])                                \
+	  __builtin_abort ();                                                  \
+	array8_##NUM[i]                                                        \
+	  = (TYPE) (array2_##NUM[i] * array7_##NUM[i] + array8_##NUM[i]);      \
+	if (array5_##NUM[i] != array8_##NUM[i])                                \
+	  __builtin_abort ();                                                  \
+      }                                                                        \
+  }
+
+int __attribute__ ((optimize (0))) main ()
+{
+  TEST_LOOP (int8_t, 7)
+  TEST_LOOP (uint8_t, 7)
+  TEST_LOOP (int16_t, 7)
+  TEST_LOOP (uint16_t, 7)
+  TEST_LOOP (int32_t, 7)
+  TEST_LOOP (uint32_t, 7)
+  TEST_LOOP (int64_t, 7)
+  TEST_LOOP (uint64_t, 7)
+
+  TEST_LOOP (int8_t, 16)
+  TEST_LOOP (uint8_t, 16)
+  TEST_LOOP (int16_t, 16)
+  TEST_LOOP (uint16_t, 16)
+  TEST_LOOP (int32_t, 16)
+  TEST_LOOP (uint32_t, 16)
+  TEST_LOOP (int64_t, 16)
+  TEST_LOOP (uint64_t, 16)
+
+  TEST_LOOP (int8_t, 77)
+  TEST_LOOP (uint8_t, 77)
+  TEST_LOOP (int16_t, 77)
+  TEST_LOOP (uint16_t, 77)
+  TEST_LOOP (int32_t, 77)
+  TEST_LOOP (uint32_t, 77)
+  TEST_LOOP (int64_t, 77)
+  TEST_LOOP (uint64_t, 77)
+
+  TEST_LOOP (int8_t, 128)
+  TEST_LOOP (uint8_t, 128)
+  TEST_LOOP (int16_t, 128)
+  TEST_LOOP (uint16_t, 128)
+  TEST_LOOP (int32_t, 128)
+  TEST_LOOP (uint32_t, 128)
+  TEST_LOOP (int64_t, 128)
+  TEST_LOOP (uint64_t, 128)
+
+  TEST_LOOP (int8_t, 15641)
+  TEST_LOOP (uint8_t, 15641)
+  TEST_LOOP (int16_t, 15641)
+  TEST_LOOP (uint16_t, 15641)
+  TEST_LOOP (int32_t, 15641)
+  TEST_LOOP (uint32_t, 15641)
+  TEST_LOOP (int64_t, 15641)
+  TEST_LOOP (uint64_t, 15641)
+
+  TEST_LOOP (int8_t, 795)
+  TEST_LOOP (uint8_t, 795)
+  TEST_LOOP (int16_t, 795)
+  TEST_LOOP (uint16_t, 795)
+  TEST_LOOP (int32_t, 795)
+  TEST_LOOP (uint32_t, 795)
+  TEST_LOOP (int64_t, 795)
+  TEST_LOOP (uint64_t, 795)
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index c0ab0dc..bf03570 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -69,6 +69,8 @@ foreach op $AUTOVEC_TEST_OPTS {
     "" "$op"
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/unop/*.\[cS\]]] \
     "" "$op"
+  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/ternop/*.\[cS\]]] \
+    "" "$op"
 }
 
 # VLS-VLMAX tests