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| author | Andrew Pinski <apinski@marvell.com> | 2020-02-08 15:57:54 +0000 |
|---|---|---|
| committer | Andrew Pinski <apinski@marvell.com> | 2020-02-08 15:48:06 -0800 |
| commit | c2a4bf2d6edde8b148421668a4c07c844b994271 (patch) | |
| tree | 6b67937e3ef6af840977f62d1005ed88b53bd37e /gcc | |
| parent | 4b39d801b2698d0f756231f6f8fa0be5a36f0c05 (diff) | |
| download | gcc-c2a4bf2d6edde8b148421668a4c07c844b994271.zip gcc-c2a4bf2d6edde8b148421668a4c07c844b994271.tar.gz gcc-c2a4bf2d6edde8b148421668a4c07c844b994271.tar.bz2 | |
aarch64: fix strict alignment for vector load/stores (PR 91927)
Hi,
The problem here is that the vector mode version of movmisalign<mode>
was only conditionalized on if SIMD was enabled instead of being
also conditionalized on STRICT_ALIGNMENT too.
Applied as pre-approved in the bug report by Richard Sandiford
after a bootstrap/test on aarch64-linux-gnu.
Thanks,
Andrew Pinski
ChangeLog:
PR target/91927
* config/aarch64/aarch64-simd.md (movmisalign<mode>): Check
STRICT_ALIGNMENT also.
testsuite/ChangeLog:
PR target/91927
* gcc.target/aarch64/pr91927.c: New testcase.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr91927.c | 38 |
4 files changed, 50 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0ae8c54..b46ea4f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-02-08 Andrew Pinski <apinski@marvell.com> + + PR target/91927 + * config/aarch64/aarch64-simd.md (movmisalign<mode>): Check + STRICT_ALIGNMENT also. + 2020-02-08 Jim Wilson <jimw@sifive.com> PR target/93532 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index c8e1012..4c651f4 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -41,7 +41,7 @@ (define_expand "movmisalign<mode>" [(set (match_operand:VALL 0 "nonimmediate_operand") (match_operand:VALL 1 "general_operand"))] - "TARGET_SIMD" + "TARGET_SIMD && !STRICT_ALIGNMENT" { /* This pattern is not permitted to fail during expansion: if both arguments are non-registers (e.g. memory := constant, which can be created by the diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b9548b3..c47f3fb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-02-08 Andrew Pinski <apinski@marvel.com> + + PR target/91927 + * gcc.target/aarch64/pr91927.c: New testcase. + 2020-02-08 Peter Bergner <bergner@linux.ibm.com> PR target/93136 diff --git a/gcc/testsuite/gcc.target/aarch64/pr91927.c b/gcc/testsuite/gcc.target/aarch64/pr91927.c new file mode 100644 index 0000000..f5cde1a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr91927.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-mstrict-align -O3" } */ + +#define NULL 0 + +typedef unsigned uint32_t; +typedef struct __attribute__((__packed__)) +{ + uint32_t nTagID; + uint32_t nValueBufferSize; + uint32_t nValueLength; + +} PropertyTags_t; + +typedef struct +{ + char *szName; + uint32_t nBufferSize; + uint32_t nLength; + +} Something_t; + +void SetTag(PropertyTags_t *pTag, uint32_t nBufferSize, uint32_t nLength); + +void TestCase(Something_t *pSome, uint32_t nBufferSize, uint32_t nLength) +{ + if (pSome != NULL) + { + PropertyTags_t sTag = { 0 }; + + SetTag(&sTag, nBufferSize, nLength); + + pSome->nBufferSize = sTag.nValueBufferSize; + pSome->nLength = sTag.nValueLength; + } +} + +/* { dg-final { scan-assembler-not "ldr\td" } } */ |