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author | Ulrich Weigand <uweigand@de.ibm.com> | 2008-08-05 13:53:20 +0000 |
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committer | Ulrich Weigand <uweigand@gcc.gnu.org> | 2008-08-05 13:53:20 +0000 |
commit | 9e071d06dfb8dbd1e2f76f26c918bce0a1e5fb9e (patch) | |
tree | 9408472c21f527ea51e2804155c844ded6a42836 /gcc | |
parent | 21f560ba8e287996eb0af332ba965e7d6e62a77e (diff) | |
download | gcc-9e071d06dfb8dbd1e2f76f26c918bce0a1e5fb9e.zip gcc-9e071d06dfb8dbd1e2f76f26c918bce0a1e5fb9e.tar.gz gcc-9e071d06dfb8dbd1e2f76f26c918bce0a1e5fb9e.tar.bz2 |
spu.h (CANNOT_CHANGE_MODE_CLASS): Allow (multi)word-sized SUBREG of multi-word hard register.
* config/spu/spu.h (CANNOT_CHANGE_MODE_CLASS): Allow (multi)word-sized
SUBREG of multi-word hard register.
* config/spu/spu.c (valid_subreg): Likewise.
(adjust_operand): Handle SUBREGs of multi-word hard registers.
From-SVN: r138711
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 7 | ||||
-rw-r--r-- | gcc/config/spu/spu.c | 9 | ||||
-rw-r--r-- | gcc/config/spu/spu.h | 1 |
3 files changed, 14 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 02ca433..10385d9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2008-08-05 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> + + * config/spu/spu.h (CANNOT_CHANGE_MODE_CLASS): Allow (multi)word-sized + SUBREG of multi-word hard register. + * config/spu/spu.c (valid_subreg): Likewise. + (adjust_operand): Handle SUBREGs of multi-word hard registers. + 2008-08-04 Richard Guenther <rguenther@suse.de> * tree-ssa-loop-ivopts.c (add_iv_value_candidates): Also add diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c index 83bd9f5..b40d12c 100644 --- a/gcc/config/spu/spu.c +++ b/gcc/config/spu/spu.c @@ -419,7 +419,8 @@ valid_subreg (rtx op) enum machine_mode im = GET_MODE (SUBREG_REG (op)); return om != VOIDmode && im != VOIDmode && (GET_MODE_SIZE (im) == GET_MODE_SIZE (om) - || (GET_MODE_SIZE (im) <= 4 && GET_MODE_SIZE (om) <= 4)); + || (GET_MODE_SIZE (im) <= 4 && GET_MODE_SIZE (om) <= 4) + || (GET_MODE_SIZE (im) >= 16 && GET_MODE_SIZE (om) >= 16)); } /* When insv and ext[sz]v ar passed a TI SUBREG, we want to strip it off @@ -429,8 +430,10 @@ adjust_operand (rtx op, HOST_WIDE_INT * start) { enum machine_mode mode; int op_size; - /* Strip any SUBREG */ - if (GET_CODE (op) == SUBREG) + /* Strip any paradoxical SUBREG. */ + if (GET_CODE (op) == SUBREG + && (GET_MODE_BITSIZE (GET_MODE (op)) + > GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op))))) { if (start) *start -= diff --git a/gcc/config/spu/spu.h b/gcc/config/spu/spu.h index 729e0d7..4180c4e 100644 --- a/gcc/config/spu/spu.h +++ b/gcc/config/spu/spu.h @@ -263,6 +263,7 @@ enum reg_class { only true for SPU. */ #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ ((GET_MODE_SIZE (FROM) > 4 || GET_MODE_SIZE (TO) > 4) \ + && (GET_MODE_SIZE (FROM) < 16 || GET_MODE_SIZE (TO) < 16) \ && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)) #define REGISTER_TARGET_PRAGMAS() do { \ |