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author | Raphael Moreira Zinsly <rzinsly@ventanamicro.com> | 2023-05-19 20:54:34 -0600 |
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committer | Jeff Law <jlaw@ventanamicro.com> | 2023-05-19 20:54:34 -0600 |
commit | 9000da00dd70988f30d43806bae33b22ee6b9904 (patch) | |
tree | 5bb494d86dff0036db26e18dd61487bc4ba79470 /gcc | |
parent | 5df01f89b7f49c2750de4acf3a9b93a08210c627 (diff) | |
download | gcc-9000da00dd70988f30d43806bae33b22ee6b9904.zip gcc-9000da00dd70988f30d43806bae33b22ee6b9904.tar.gz gcc-9000da00dd70988f30d43806bae33b22ee6b9904.tar.bz2 |
RISC-V: Fix CTZ unnecessary sign extension [PR #106888]
Changes since v1:
- Remove subreg from operand 1.
-- >8 --
We were not able to match the CTZ sign extend pattern on RISC-V
because it gets optimized to zero extend and/or to ANDI patterns.
For the ANDI case, combine scrambles the RTL and generates the
extension by using subregs.
gcc/ChangeLog:
PR target/106888
* config/riscv/bitmanip.md
(<bitmanip_optab>disi2): Match with any_extend.
(<bitmanip_optab>disi2_sext): New pattern to match
with sign extend using an ANDI instruction.
gcc/testsuite/ChangeLog:
PR target/106888
* gcc.target/riscv/pr106888.c: New test.
* gcc.target/riscv/zbbw.c: Check for ANDI.
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/riscv/bitmanip.md | 13 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/pr106888.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/zbbw.c | 1 |
3 files changed, 25 insertions, 1 deletions
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 6f3d24a..c2a29e18 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -246,13 +246,24 @@ (define_insn "*<bitmanip_optab>disi2" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI + (any_extend:DI (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))] "TARGET_64BIT && TARGET_ZBB" "<bitmanip_insn>w\t%0,%1" [(set_attr "type" "<bitmanip_insn>") (set_attr "mode" "SI")]) +;; A SImode clz_ctz_pcnt may be extended to DImode via subreg. +(define_insn "*<bitmanip_optab>disi2_sext" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (subreg:DI + (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")) 0) + (match_operand:DI 2 "const_int_operand")))] + "TARGET_64BIT && TARGET_ZBB && ((INTVAL (operands[2]) & 0x3f) == 0x3f)" + "<bitmanip_insn>w\t%0,%1" + [(set_attr "type" "bitmanip") + (set_attr "mode" "SI")]) + (define_insn "*<bitmanip_optab>di2" [(set (match_operand:DI 0 "register_operand" "=r") (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))] diff --git a/gcc/testsuite/gcc.target/riscv/pr106888.c b/gcc/testsuite/gcc.target/riscv/pr106888.c new file mode 100644 index 0000000..77fb8e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr106888.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */ + +int +ctz (int i) +{ + int res = __builtin_ctz (i); + return res&0xffff; +} + +/* { dg-final { scan-assembler-times "ctzw" 1 } } */ +/* { dg-final { scan-assembler-not "andi" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c index 709743c..f7b2b63 100644 --- a/gcc/testsuite/gcc.target/riscv/zbbw.c +++ b/gcc/testsuite/gcc.target/riscv/zbbw.c @@ -23,3 +23,4 @@ popcount (int i) /* { dg-final { scan-assembler-times "clzw" 1 } } */ /* { dg-final { scan-assembler-times "ctzw" 1 } } */ /* { dg-final { scan-assembler-times "cpopw" 1 } } */ +/* { dg-final { scan-assembler-not "andi\t" } } */ |