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| author | Maciej W. Rozycki <macro@wdc.com> | 2020-04-02 15:43:05 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@wdc.com> | 2020-04-02 15:43:05 +0100 |
| commit | 879bc686a0aac4277532fc2aa18704c125fb0c45 (patch) | |
| tree | ce3ba5cfcd5684f387bc2b3deb7bc10046fab799 /gcc | |
| parent | 81ce375d1fdd99f9d93b00f4895eab74c3d8b54a (diff) | |
| download | gcc-879bc686a0aac4277532fc2aa18704c125fb0c45.zip gcc-879bc686a0aac4277532fc2aa18704c125fb0c45.tar.gz gcc-879bc686a0aac4277532fc2aa18704c125fb0c45.tar.bz2 | |
doc: RISC-V: Update binutils requirement to 2.30
Complement commit bfe78b08471f ("RISC-V: Using fmv.x.w/fmv.w.x rather
than fmv.x.s/fmv.s.x") and document a binutils 2.30 requirement in the
installation manual, matching the addition of fmv.x.w/fmv.w.x mnemonics
to GAS.
gcc/
* doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
<riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
2.30.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/doc/install.texi | 12 |
2 files changed, 10 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f0a9509..671411e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-04-02 Maciej W. Rozycki <macro@wdc.com> + + * doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux> + <riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to + 2.30. + 2020-04-02 Kewen Lin <linkw@gcc.gnu.org> PR tree-optimization/94401 diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 5596108..bc5259d 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -4545,8 +4545,7 @@ This configuration is intended for embedded systems. @heading riscv32-*-elf The RISC-V RV32 instruction set. This configuration is intended for embedded systems. -This (and all other RISC-V) targets are supported upstream as of the -binutils 2.28 release. +This (and all other RISC-V) targets require the binutils 2.30 release. @html <hr /> @@ -4554,8 +4553,7 @@ binutils 2.28 release. @anchor{riscv32-x-linux} @heading riscv32-*-linux The RISC-V RV32 instruction set running GNU/Linux. -This (and all other RISC-V) targets are supported upstream as of the -binutils 2.28 release. +This (and all other RISC-V) targets require the binutils 2.30 release. @html <hr /> @@ -4564,8 +4562,7 @@ binutils 2.28 release. @heading riscv64-*-elf The RISC-V RV64 instruction set. This configuration is intended for embedded systems. -This (and all other RISC-V) targets are supported upstream as of the -binutils 2.28 release. +This (and all other RISC-V) targets require the binutils 2.30 release. @html <hr /> @@ -4573,8 +4570,7 @@ binutils 2.28 release. @anchor{riscv64-x-linux} @heading riscv64-*-linux The RISC-V RV64 instruction set running GNU/Linux. -This (and all other RISC-V) targets are supported upstream as of the -binutils 2.28 release. +This (and all other RISC-V) targets require the binutils 2.30 release. @html <hr /> |