invoke.texi: Document -march=74kf3_2.

gcc/
2007-07-03  David Ung  <davidu@mips.com>
	    Richard Sandiford  <richard@codesourcery.com>

	* doc/invoke.texi: Document -march=74kf3_2.
	* config/mips/mips.h (PROCESSOR_74KF3_2): New processor_type.
	(TUNE_74K): Check for it.
	* config/mips/mips.c (mips_cpu_info): Add 74kf3_2.
	(mips_rtx_cost_data): Add an entry for PROCESSOR_74KF3_2.
	* config/mips/mips.md (cpu): Add 74kf3_2.
	* config/mips/74k.md (r74k_int_logical, r74k_int_arith, r74k_int_nop)
	(r74k_int_cmove, r74k_int_mult, r74k_int_mul3, r74k_int_mfhilo)
	(r74k_int_mthilo, r74k_int_div, r74k_int_call, r74k_int_jump)
	(r74k_int_load, r74k_int_store, r74k_unknown, r74k_multi): Add
	74kf3_2 to the CPU list.
	(r74kf3_2_fadd, r74kf3_2_fmove, r74kf3_2_fload, r74kf3_2_fstore)
	(r74kf3_2_fmul_sf, r74kf3_2_fmul_df, r74kf3_2_fdiv_sf)
	(r74kf3_2_fdiv_df, r74kf3_2_frsqrt_sf, r74kf3_2_frsqrt_df)
	(r74kf3_2_fcmp, r74kf3_2_fcvt, r74kf3_2_fxfer_to_c1)
	(r74kf3_2_fxfer_from_c1): New insn reservations.

Co-Authored-By: Richard Sandiford <richard@codesourcery.com>

From-SVN: r126267

6 files changed, 136 insertions, 21 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c65552c..e58836c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,23 @@
+2007-07-03  David Ung  <davidu@mips.com>
+	    Richard Sandiford  <richard@codesourcery.com>
+
+	* doc/invoke.texi: Document -march=74kf3_2.
+	* config/mips/mips.h (PROCESSOR_74KF3_2): New processor_type.
+	(TUNE_74K): Check for it.
+	* config/mips/mips.c (mips_cpu_info): Add 74kf3_2.
+	(mips_rtx_cost_data): Add an entry for PROCESSOR_74KF3_2.
+	* config/mips/mips.md (cpu): Add 74kf3_2.
+	* config/mips/74k.md (r74k_int_logical, r74k_int_arith, r74k_int_nop)
+	(r74k_int_cmove, r74k_int_mult, r74k_int_mul3, r74k_int_mfhilo)
+	(r74k_int_mthilo, r74k_int_div, r74k_int_call, r74k_int_jump)
+	(r74k_int_load, r74k_int_store, r74k_unknown, r74k_multi): Add
+	74kf3_2 to the CPU list.
+	(r74kf3_2_fadd, r74kf3_2_fmove, r74kf3_2_fload, r74kf3_2_fstore)
+	(r74kf3_2_fmul_sf, r74kf3_2_fmul_df, r74kf3_2_fdiv_sf)
+	(r74kf3_2_fdiv_df, r74kf3_2_frsqrt_sf, r74kf3_2_frsqrt_df)
+	(r74kf3_2_fcmp, r74kf3_2_fcvt, r74kf3_2_fxfer_to_c1)
+	(r74kf3_2_fxfer_from_c1): New insn reservations.
+
 2007-07-03  Richard Sandiford  <richard@codesourcery.com>
 	    David Ung  <davidu@mips.com>
 
diff --git a/gcc/config/mips/74k.md b/gcc/config/mips/74k.md
index 2f237c9..1d3aaa4 100644
--- a/gcc/config/mips/74k.md
+++ b/gcc/config/mips/74k.md
@@ -40,74 +40,74 @@
 ;;    sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh,
 ;;    xor, xori
 (define_insn_reservation "r74k_int_arith" 2
-  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
        (eq_attr "type" "arith,const,shift,slt,clz"))
   "r74k_alu")
 
 (define_insn_reservation "r74k_int_nop" 0
-  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
        (eq_attr "type" "nop"))
   "nothing")
 
 (define_insn_reservation "r74k_int_cmove" 4
-  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
        (eq_attr "type" "condmove"))
   "r74k_agen*2")
 
 ;; MDU: fully pipelined multiplier
 ;; mult, madd, msub - delivers result to hi/lo in 4 cycle (pipelined)
 (define_insn_reservation "r74k_int_mult" 4
-  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
        (eq_attr "type" "imul,imadd"))
   "r74k_alu+r74k_mul")
 
 ;; mul - delivers result to general register in 7 cycles
 (define_insn_reservation "r74k_int_mul3" 7
-  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
        (eq_attr "type" "imul3"))
   "r74k_alu+r74k_mul")
 
 ;; mfhi, mflo, mflhxu - deliver result to gpr in 7 cycles
 (define_insn_reservation "r74k_int_mfhilo" 7
-  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
        (eq_attr "type" "mfhilo"))
   "r74k_alu+r74k_mul")
 
 ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
 (define_insn_reservation "r74k_int_mthilo" 7
-  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
        (eq_attr "type" "mthilo"))
   "r74k_alu+r74k_mul")
 
 ;; div - default to 50 cycles for 32bit operands.  Faster for 8 bit,
 ;; but is tricky to identify.
 (define_insn_reservation "r74k_int_div" 50
-  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
        (eq_attr "type" "idiv"))
   "r74k_alu+r74k_mul*50")
 
 ;; call
 (define_insn_reservation "r74k_int_call" 1
-  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
        (eq_attr "type" "call"))
   "r74k_agen")
 
 ;; branch/jump
 (define_insn_reservation "r74k_int_jump" 1
-  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
        (eq_attr "type" "branch,jump"))
   "r74k_agen")
 
 ;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
 ;; prefetch: prefetch, prefetchx
 (define_insn_reservation "r74k_int_load" 3 
-  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
        (eq_attr "type" "load,prefetch,prefetchx"))
   "r74k_agen")
 
 ;; stores
 (define_insn_reservation "r74k_int_store" 1
-  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
        (and (eq_attr "type" "store")
             (eq_attr "mode" "!unknown")))
   "r74k_agen")
@@ -118,12 +118,12 @@
 ;;            affects scheduling via log links, but not used here).
 ;;
 (define_insn_reservation "r74k_unknown" 1 
-  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
        (eq_attr "type" "unknown"))
   "r74k_alu")
 
 (define_insn_reservation "r74k_multi" 10
-  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
        (eq_attr "type" "multi"))
   "(r74k_alu+r74k_agen)*10")
 
@@ -170,6 +170,11 @@
        (eq_attr "type" "fadd,fabs,fneg"))
   "r74k_fpu_arith*2")
 
+(define_insn_reservation "r74kf3_2_fadd" 6
+  (and (eq_attr "cpu" "74kf3_2")
+       (eq_attr "type" "fadd,fabs,fneg"))
+  "r74k_fpu_arith")
+
 ;; fmove, fcmove
 (define_insn_reservation "r74kf1_1_fmove" 4
   (and (eq_attr "cpu" "74kf1_1")
@@ -181,6 +186,11 @@
        (eq_attr "type" "fmove"))
   "r74k_fpu_arith*2")
 
+(define_insn_reservation "r74kf3_2_fmove" 6
+  (and (eq_attr "cpu" "74kf3_2")
+       (eq_attr "type" "fmove"))
+  "r74k_fpu_arith")
+
 ;; fload
 (define_insn_reservation "r74kf1_1_fload" 4
   (and (eq_attr "cpu" "74kf1_1")
@@ -192,6 +202,11 @@
        (eq_attr "type" "fpload,fpidxload"))
   "r74k_agen+(r74k_fpu_ldst*2)")
 
+(define_insn_reservation "r74kf3_2_fload" 6
+  (and (eq_attr "cpu" "74kf3_2")
+       (eq_attr "type" "fpload,fpidxload"))
+  "r74k_agen+r74k_fpu_ldst")
+
 ;; fstore
 (define_insn_reservation "r74kf1_1_fstore" 1
   (and (eq_attr "cpu" "74kf1_1")
@@ -203,6 +218,11 @@
        (eq_attr "type" "fpstore,fpidxstore"))
   "r74k_agen+(r74k_fpu_ldst*2)")
 
+(define_insn_reservation "r74kf3_2_fstore" 1
+  (and (eq_attr "cpu" "74kf3_2")
+       (eq_attr "type" "fpstore,fpidxstore"))
+  "r74k_agen+r74k_fpu_ldst")
+
 ;; fmul, fmadd
 (define_insn_reservation "r74kf1_1_fmul_sf" 4
   (and (eq_attr "cpu" "74kf1_1")
@@ -216,6 +236,12 @@
 	    (eq_attr "mode" "SF")))
   "r74k_fpu_arith*2")
 
+(define_insn_reservation "r74kf3_2_fmul_sf" 6
+  (and (eq_attr "cpu" "74kf3_2")
+       (and (eq_attr "type" "fmul,fmadd")
+	    (eq_attr "mode" "SF")))
+  "r74k_fpu_arith")
+
 (define_insn_reservation "r74kf1_1_fmul_df" 5
   (and (eq_attr "cpu" "74kf1_1")
        (and (eq_attr "type" "fmul,fmadd")
@@ -228,6 +254,12 @@
 	    (eq_attr "mode" "DF")))
   "r74k_fpu_arith*4")
 
+(define_insn_reservation "r74kf3_2_fmul_df" 7
+  (and (eq_attr "cpu" "74kf3_2")
+       (and (eq_attr "type" "fmul,fmadd")
+	    (eq_attr "mode" "DF")))
+  "r74k_fpu_arith*2")
+
 ;; fdiv, fsqrt
 (define_insn_reservation "r74kf1_1_fdiv_sf" 17
   (and (eq_attr "cpu" "74kf1_1")
@@ -241,6 +273,12 @@
 	    (eq_attr "mode" "SF")))
   "r74k_fpu_arith*28")
 
+(define_insn_reservation "r74kf3_2_fdiv_sf" 25
+  (and (eq_attr "cpu" "74kf3_2")
+       (and (eq_attr "type" "fdiv,fsqrt")
+	    (eq_attr "mode" "SF")))
+  "r74k_fpu_arith*14")
+
 (define_insn_reservation "r74kf1_1_fdiv_df" 32
   (and (eq_attr "cpu" "74kf1_1")
        (and (eq_attr "type" "fdiv,fsqrt")
@@ -253,6 +291,12 @@
 	    (eq_attr "mode" "DF")))
   "r74k_fpu_arith*58")
 
+(define_insn_reservation "r74kf3_2_fdiv_df" 48
+  (and (eq_attr "cpu" "74kf3_2")
+       (and (eq_attr "type" "fdiv,fsqrt")
+	    (eq_attr "mode" "DF")))
+  "r74k_fpu_arith*29")
+
 ;; frsqrt
 (define_insn_reservation "r74kf1_1_frsqrt_sf" 17
   (and (eq_attr "cpu" "74kf1_1")
@@ -266,6 +310,12 @@
 	    (eq_attr "mode" "SF")))
   "r74k_fpu_arith*28")
 
+(define_insn_reservation "r74kf3_2_frsqrt_sf" 25
+  (and (eq_attr "cpu" "74kf3_2")
+       (and (eq_attr "type" "frsqrt")
+	    (eq_attr "mode" "SF")))
+  "r74k_fpu_arith*14")
+
 (define_insn_reservation "r74kf1_1_frsqrt_df" 36
   (and (eq_attr "cpu" "74kf1_1")
        (and (eq_attr "type" "frsqrt")
@@ -278,6 +328,12 @@
 	    (eq_attr "mode" "DF")))
   "r74k_fpu_arith*62")
 
+(define_insn_reservation "r74kf3_2_frsqrt_df" 54
+  (and (eq_attr "cpu" "74kf3_2")
+       (and (eq_attr "type" "frsqrt")
+	    (eq_attr "mode" "DF")))
+  "r74k_fpu_arith*31")
+
 ;; fcmp
 (define_insn_reservation "r74kf1_1_fcmp" 4
   (and (eq_attr "cpu" "74kf1_1")
@@ -289,6 +345,11 @@
        (eq_attr "type" "fcmp"))
   "r74k_fpu_arith*2")
 
+(define_insn_reservation "r74kf3_2_fcmp" 6
+  (and (eq_attr "cpu" "74kf3_2")
+       (eq_attr "type" "fcmp"))
+  "r74k_fpu_arith")
+
 ;; fcvt
 (define_insn_reservation "r74kf1_1_fcvt" 4
   (and (eq_attr "cpu" "74kf1_1")
@@ -300,6 +361,11 @@
        (eq_attr "type" "fcvt"))
   "r74k_fpu_arith*2")
 
+(define_insn_reservation "r74kf3_2_fcvt" 6
+  (and (eq_attr "cpu" "74kf3_2")
+       (eq_attr "type" "fcvt"))
+  "r74k_fpu_arith")
+
 ;; fxfer (MTC1, DMTC1: latency is 4) (MFC1, DMFC1: latency is 1)
 (define_insn_reservation "r74kf1_1_fxfer_to_c1" 4
   (and (eq_attr "cpu" "74kf1_1")
@@ -311,6 +377,11 @@
        (eq_attr "type" "mtc"))
   "r74k_fpu_arith*2")
 
+(define_insn_reservation "r74kf3_2_fxfer_to_c1" 6
+  (and (eq_attr "cpu" "74kf3_2")
+       (eq_attr "type" "mtc"))
+  "r74k_fpu_arith")
+
 (define_insn_reservation "r74kf1_1_fxfer_from_c1" 1
   (and (eq_attr "cpu" "74kf1_1")
        (eq_attr "type" "mfc"))
@@ -320,3 +391,8 @@
   (and (eq_attr "cpu" "74kf2_1")
        (eq_attr "type" "mfc"))
   "r74k_fpu_arith*2")
+
+(define_insn_reservation "r74kf3_2_fxfer_from_c1" 1
+  (and (eq_attr "cpu" "74kf3_2")
+       (eq_attr "type" "mfc"))
+  "r74k_fpu_arith")
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 8adf7c3..3331b9e 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -799,6 +799,7 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
   { "74kf1_1", PROCESSOR_74KF1_1, 33 },
   { "74kfx", PROCESSOR_74KF1_1, 33 },
   { "74kx", PROCESSOR_74KF1_1, 33 },
+  { "74kf3_2", PROCESSOR_74KF3_2, 33 },
 
   /* MIPS64 */
   { "5kc", PROCESSOR_5KC, 64 },
@@ -978,6 +979,19 @@ static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
                        1,           /* branch_cost */
                        4            /* memory_latency */
     },
+    { /* 74KF3_2 */
+      COSTS_N_INSNS (6),            /* fp_add */
+      COSTS_N_INSNS (6),            /* fp_mult_sf */
+      COSTS_N_INSNS (7),            /* fp_mult_df */
+      COSTS_N_INSNS (25),           /* fp_div_sf */
+      COSTS_N_INSNS (48),           /* fp_div_df */
+      COSTS_N_INSNS (5),            /* int_mult_si */
+      COSTS_N_INSNS (5),            /* int_mult_di */
+      COSTS_N_INSNS (41),           /* int_div_si */
+      COSTS_N_INSNS (41),           /* int_div_di */
+                       1,           /* branch_cost */
+                       4            /* memory_latency */
+    },
     { /* M4k */
       DEFAULT_COSTS
     },
@@ -10798,6 +10812,7 @@ mips_issue_rate (void)
     case PROCESSOR_74KC:
     case PROCESSOR_74KF2_1:
     case PROCESSOR_74KF1_1:
+    case PROCESSOR_74KF3_2:
     case PROCESSOR_R4130:
     case PROCESSOR_R5400:
     case PROCESSOR_R5500:
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index a07af18..8338829 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -46,6 +46,7 @@ enum processor_type {
   PROCESSOR_74KC,
   PROCESSOR_74KF2_1,
   PROCESSOR_74KF1_1,
+  PROCESSOR_74KF3_2,
   PROCESSOR_M4K,
   PROCESSOR_R3900,
   PROCESSOR_R6000,
@@ -250,7 +251,8 @@ extern const struct mips_rtx_cost_data *mips_cost;
 				     || mips_tune == PROCESSOR_SB1A)
 #define TUNE_74K                    (mips_tune == PROCESSOR_74KC	\
 				     || mips_tune == PROCESSOR_74KF2_1	\
-				     || mips_tune == PROCESSOR_74KF1_1)
+				     || mips_tune == PROCESSOR_74KF1_1  \
+				     || mips_tune == PROCESSOR_74KF3_2)
 
 /* True if the pre-reload scheduler should try to create chains of
    multiply-add or multiply-subtract instructions.  For example,
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index e663abd..1d72ff6 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -397,7 +397,7 @@
 ;; Attribute describing the processor.  This attribute must match exactly
 ;; with the processor_type enumeration in mips.h.
 (define_attr "cpu"
-  "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
+  "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
   (const (symbol_ref "mips_tune")))
 
 ;; The type of hardware hazard associated with this instruction.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 1a9c1aa..2b5fff2 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -11428,7 +11428,7 @@ The processor names are:
 @samp{24kc}, @samp{24kf2_1}, @samp{24kf1_1},
 @samp{24kec}, @samp{24kef2_1}, @samp{24kef1_1},
 @samp{34kc}, @samp{34kf2_1}, @samp{34kf1_1},
-@samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1},
+@samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1}, @samp{74kf3_2},
 @samp{m4k},
 @samp{orion},
 @samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
@@ -11447,11 +11447,13 @@ In processor names, a final @samp{000} can be abbreviated as @samp{k}
 @samp{vr} may be written @samp{r}.
 
 Names of the form @samp{@var{n}f2_1} refer to processors with
-FPUs clocked at half the rate of the core.  Names of the form
+FPUs clocked at half the rate of the core, names of the form
 @samp{@var{n}f1_1} refer to processors with FPUs clocked at the same
-rate as the core.  For compatibility reasons, @samp{@var{n}f} is
-accepted as a synonym for @samp{@var{n}f2_1} while @samp{@var{n}x} and
-@samp{@var{b}fx} are accepted as synonyms for @samp{@var{n}f1_1}.
+rate as the core, and names of the form @samp{@var{n}f3_2} refer to
+processors with FPUs clocked a ratio of 3:2 with respect to the core.
+For compatibility reasons, @samp{@var{n}f} is accepted as a synonym
+for @samp{@var{n}f2_1} while @samp{@var{n}x} and @samp{@var{b}fx} are
+accepted as synonyms for @samp{@var{n}f1_1}.
 
 GCC defines two macros based on the value of this option.  The first
 is @samp{_MIPS_ARCH}, which gives the name of target architecture, as