RISC-V: Add vnclip C API tests

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/vnclip_wv-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_m-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_m-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_m-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_mu-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_mu-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_mu-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_tu-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_tu-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_tu-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_tum-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_tum-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_tum-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_tumu-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_tumu-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wv_tumu-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_m-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_m-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_m-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_mu-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_mu-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_mu-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_tu-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_tu-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_tu-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_tum-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_tum-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_tum-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_tumu-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_tumu-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclip_wx_tumu-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_m-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_m-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_m-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_mu-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_mu-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_mu-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_tu-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_tu-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_tu-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_tum-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_tum-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_tum-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_tumu-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_tumu-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wv_tumu-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_m-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_m-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_m-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_mu-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_mu-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_mu-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_tu-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_tu-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_tu-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_tum-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_tum-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_tum-3.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_tumu-1.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_tumu-2.c: New test.
	* gcc.target/riscv/rvv/base/vnclipu_wx_tumu-3.c: New test.

72 files changed, 7992 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv-1.c
new file mode 100644
index 0000000..fb0aa33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8(vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4(vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2(vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1(vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2(vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2(op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4(vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4(op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4(vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4(op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2(vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2(op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1(vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1(op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2(vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2(op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4(vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4(op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2(vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2(op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1(vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1(op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2(vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2(op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4(vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4(op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv-2.c
new file mode 100644
index 0000000..8551696
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8(vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8(op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4(vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4(op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2(vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2(op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1(vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1(op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2(vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2(op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4(vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4(op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4(vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4(op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2(vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2(op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1(vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1(op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2(vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2(op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4(vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4(op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2(vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2(op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1(vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1(op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2(vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2(op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4(vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4(op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv-3.c
new file mode 100644
index 0000000..852d3f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8(vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8(op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4(vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4(op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2(vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2(op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1(vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1(op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2(vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2(op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4(vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4(op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4(vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4(op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2(vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2(op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1(vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1(op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2(vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2(op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4(vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4(op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2(vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2(op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1(vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1(op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2(vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2(op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4(vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4(op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_m-1.c
new file mode 100644
index 0000000..5f8d6a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_m-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_m(vbool64_t mask,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_m(mask,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_m(vbool32_t mask,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_m(mask,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_m(vbool16_t mask,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_m(mask,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_m(vbool8_t mask,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_m(mask,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_m(vbool4_t mask,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_m(mask,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_m(vbool2_t mask,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_m(mask,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_m(vbool64_t mask,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_m(mask,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_m(vbool32_t mask,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_m(mask,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_m(vbool16_t mask,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_m(mask,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_m(vbool8_t mask,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_m(mask,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_m(vbool4_t mask,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_m(mask,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_m(vbool64_t mask,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_m(mask,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_m(vbool32_t mask,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_m(mask,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_m(vbool16_t mask,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_m(mask,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_m(vbool8_t mask,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_m(mask,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_m-2.c
new file mode 100644
index 0000000..ddb615d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_m-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_m(vbool64_t mask,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_m(mask,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_m(vbool32_t mask,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_m(mask,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_m(vbool16_t mask,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_m(mask,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_m(vbool8_t mask,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_m(mask,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_m(vbool4_t mask,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_m(mask,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_m(vbool2_t mask,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_m(mask,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_m(vbool64_t mask,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_m(mask,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_m(vbool32_t mask,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_m(mask,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_m(vbool16_t mask,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_m(mask,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_m(vbool8_t mask,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_m(mask,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_m(vbool4_t mask,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_m(mask,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_m(vbool64_t mask,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_m(mask,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_m(vbool32_t mask,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_m(mask,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_m(vbool16_t mask,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_m(mask,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_m(vbool8_t mask,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_m(mask,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_m-3.c
new file mode 100644
index 0000000..87ac646
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_m-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_m(vbool64_t mask,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_m(mask,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_m(vbool32_t mask,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_m(mask,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_m(vbool16_t mask,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_m(mask,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_m(vbool8_t mask,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_m(mask,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_m(vbool4_t mask,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_m(mask,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_m(vbool2_t mask,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_m(mask,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_m(vbool64_t mask,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_m(mask,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_m(vbool32_t mask,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_m(mask,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_m(vbool16_t mask,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_m(mask,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_m(vbool8_t mask,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_m(mask,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_m(vbool4_t mask,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_m(mask,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_m(vbool64_t mask,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_m(mask,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_m(vbool32_t mask,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_m(mask,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_m(vbool16_t mask,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_m(mask,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_m(vbool8_t mask,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_m(mask,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_mu-1.c
new file mode 100644
index 0000000..ce6696c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_mu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_mu-2.c
new file mode 100644
index 0000000..dd03316
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_mu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_mu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_mu-3.c
new file mode 100644
index 0000000..ea5e2ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_mu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_mu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tu-1.c
new file mode 100644
index 0000000..1df7e95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_tu(vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_tu(vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_tu(vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_tu(vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_tu(merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_tu(vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_tu(merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_tu(vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_tu(vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_tu(vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_tu(vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_tu(merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_tu(vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_tu(merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_tu(vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_tu(merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_tu(vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_tu(vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_tu(merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_tu(vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_tu(merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_tu(vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_tu(merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tu-2.c
new file mode 100644
index 0000000..521c65e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_tu(vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_tu(merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_tu(vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_tu(merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_tu(vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_tu(merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_tu(vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_tu(merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_tu(vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_tu(merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_tu(vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_tu(merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_tu(vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_tu(merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_tu(vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_tu(merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_tu(vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_tu(merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_tu(vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_tu(merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_tu(vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_tu(merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_tu(vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_tu(merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_tu(vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_tu(merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_tu(vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_tu(merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_tu(vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_tu(merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tu-3.c
new file mode 100644
index 0000000..705d951
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_tu(vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_tu(merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_tu(vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_tu(merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_tu(vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_tu(merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_tu(vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_tu(merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_tu(vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_tu(merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_tu(vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_tu(merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_tu(vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_tu(merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_tu(vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_tu(merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_tu(vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_tu(merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_tu(vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_tu(merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_tu(vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_tu(merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_tu(vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_tu(merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_tu(vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_tu(merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_tu(vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_tu(merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_tu(vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_tu(merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tum-1.c
new file mode 100644
index 0000000..463eea3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tum-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tum-2.c
new file mode 100644
index 0000000..d74b1c43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tum-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_tum(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tum-3.c
new file mode 100644
index 0000000..eaf3094
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tum-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_tum(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tumu-1.c
new file mode 100644
index 0000000..1fe7ff6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tumu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tumu-2.c
new file mode 100644
index 0000000..67cdcd3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tumu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tumu-3.c
new file mode 100644
index 0000000..99086d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tumu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf8_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnclip_wv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnclip_wv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnclip_wv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i8m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnclip_wv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnclip_wv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnclip_wv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i16m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnclip_wv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnclip_wv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnclip_wv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclip_wv_i32m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx-1.c
new file mode 100644
index 0000000..afcb922
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8(vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4(vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2(vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1(vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2(vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2(op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4(vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4(op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4(vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4(op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2(vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2(op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1(vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1(op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2(vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2(op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4(vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4(op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2(vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2(op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1(vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1(op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2(vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2(op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4(vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4(op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx-2.c
new file mode 100644
index 0000000..957cf7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8(vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8(op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4(vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4(op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2(vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2(op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1(vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1(op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2(vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2(op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4(vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4(op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4(vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4(op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2(vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2(op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1(vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1(op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2(vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2(op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4(vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4(op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2(vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2(op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1(vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1(op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2(vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2(op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4(vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4(op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx-3.c
new file mode 100644
index 0000000..91a6730
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8(vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8(op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4(vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4(op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2(vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2(op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1(vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1(op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2(vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2(op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4(vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4(op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4(vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4(op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2(vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2(op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1(vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1(op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2(vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2(op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4(vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4(op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2(vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2(op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1(vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1(op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2(vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2(op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4(vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4(op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_m-1.c
new file mode 100644
index 0000000..29b9504
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_m-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_m(mask,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_m(mask,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_m(mask,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_m(mask,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_m(mask,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_m(mask,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_m(mask,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_m(mask,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_m(mask,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_m(mask,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_m(mask,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_m(mask,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_m(mask,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_m(mask,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_m(mask,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_m-2.c
new file mode 100644
index 0000000..69593d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_m-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_m(mask,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_m(mask,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_m(mask,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_m(mask,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_m(mask,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_m(mask,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_m(mask,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_m(mask,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_m(mask,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_m(mask,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_m(mask,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_m(mask,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_m(mask,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_m(mask,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_m(mask,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_m-3.c
new file mode 100644
index 0000000..8243b42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_m-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_m(mask,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_m(mask,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_m(mask,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_m(mask,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_m(mask,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_m(mask,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_m(mask,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_m(mask,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_m(mask,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_m(mask,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_m(mask,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_m(mask,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_m(mask,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_m(mask,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_m(mask,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_mu-1.c
new file mode 100644
index 0000000..5f70dc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_mu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_mu-2.c
new file mode 100644
index 0000000..26bd0bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_mu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_mu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_mu-3.c
new file mode 100644
index 0000000..67804a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_mu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_mu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tu-1.c
new file mode 100644
index 0000000..e426581
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_tu(vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_tu(vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_tu(vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_tu(vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_tu(merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_tu(vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_tu(merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_tu(vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_tu(vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_tu(vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_tu(vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_tu(merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_tu(vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_tu(merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_tu(vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_tu(merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_tu(vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_tu(vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_tu(merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_tu(vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_tu(merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_tu(vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_tu(merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tu-2.c
new file mode 100644
index 0000000..ab25347
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_tu(vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_tu(merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_tu(vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_tu(merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_tu(vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_tu(merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_tu(vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_tu(merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_tu(vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_tu(merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_tu(vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_tu(merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_tu(vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_tu(merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_tu(vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_tu(merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_tu(vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_tu(merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_tu(vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_tu(merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_tu(vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_tu(merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_tu(vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_tu(merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_tu(vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_tu(merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_tu(vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_tu(merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_tu(vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_tu(merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tu-3.c
new file mode 100644
index 0000000..f9d3f59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_tu(vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_tu(merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_tu(vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_tu(merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_tu(vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_tu(merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_tu(vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_tu(merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_tu(vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_tu(merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_tu(vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_tu(merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_tu(vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_tu(merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_tu(vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_tu(merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_tu(vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_tu(merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_tu(vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_tu(merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_tu(vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_tu(merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_tu(vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_tu(merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_tu(vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_tu(merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_tu(vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_tu(merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_tu(vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_tu(merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tum-1.c
new file mode 100644
index 0000000..0c4bfdb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tum-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tum-2.c
new file mode 100644
index 0000000..9b45f7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tum-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_tum(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tum-3.c
new file mode 100644
index 0000000..7855889
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tum-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_tum(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tumu-1.c
new file mode 100644
index 0000000..cd0fef7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tumu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tumu-2.c
new file mode 100644
index 0000000..0528115
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tumu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tumu-3.c
new file mode 100644
index 0000000..631e71b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tumu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnclip_wx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf8_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnclip_wx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnclip_wx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnclip_wx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnclip_wx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnclip_wx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i8m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnclip_wx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnclip_wx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnclip_wx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnclip_wx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnclip_wx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i16m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnclip_wx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnclip_wx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnclip_wx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnclip_wx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclip_wx_i32m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv-1.c
new file mode 100644
index 0000000..452f853
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8(vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8(op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4(vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4(op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2(vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2(op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1(vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1(op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2(vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2(op1,shift,vl);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4(vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4(op1,shift,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4(vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4(op1,shift,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2(vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2(op1,shift,vl);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1(vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1(op1,shift,vl);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2(vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2(op1,shift,vl);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4(vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4(op1,shift,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2(vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2(op1,shift,vl);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1(vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1(op1,shift,vl);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2(vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2(op1,shift,vl);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4(vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4(op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv-2.c
new file mode 100644
index 0000000..28f1527
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8(vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8(op1,shift,31);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4(vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4(op1,shift,31);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2(vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2(op1,shift,31);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1(vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1(op1,shift,31);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2(vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2(op1,shift,31);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4(vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4(op1,shift,31);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4(vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4(op1,shift,31);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2(vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2(op1,shift,31);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1(vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1(op1,shift,31);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2(vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2(op1,shift,31);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4(vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4(op1,shift,31);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2(vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2(op1,shift,31);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1(vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1(op1,shift,31);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2(vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2(op1,shift,31);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4(vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4(op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv-3.c
new file mode 100644
index 0000000..7725939
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8(vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8(op1,shift,32);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4(vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4(op1,shift,32);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2(vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2(op1,shift,32);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1(vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1(op1,shift,32);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2(vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2(op1,shift,32);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4(vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4(op1,shift,32);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4(vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4(op1,shift,32);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2(vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2(op1,shift,32);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1(vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1(op1,shift,32);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2(vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2(op1,shift,32);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4(vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4(op1,shift,32);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2(vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2(op1,shift,32);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1(vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1(op1,shift,32);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2(vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2(op1,shift,32);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4(vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4(op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_m-1.c
new file mode 100644
index 0000000..6e4054b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_m-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_m(mask,op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_m(mask,op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_m(mask,op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_m(mask,op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_m(mask,op1,shift,vl);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_m(mask,op1,shift,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_m(mask,op1,shift,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_m(mask,op1,shift,vl);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_m(mask,op1,shift,vl);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_m(mask,op1,shift,vl);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_m(mask,op1,shift,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_m(mask,op1,shift,vl);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_m(mask,op1,shift,vl);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_m(mask,op1,shift,vl);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_m(mask,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_m-2.c
new file mode 100644
index 0000000..0622b0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_m-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_m(mask,op1,shift,31);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_m(mask,op1,shift,31);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_m(mask,op1,shift,31);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_m(mask,op1,shift,31);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_m(mask,op1,shift,31);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_m(mask,op1,shift,31);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_m(mask,op1,shift,31);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_m(mask,op1,shift,31);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_m(mask,op1,shift,31);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_m(mask,op1,shift,31);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_m(mask,op1,shift,31);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_m(mask,op1,shift,31);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_m(mask,op1,shift,31);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_m(mask,op1,shift,31);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_m(mask,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_m-3.c
new file mode 100644
index 0000000..91b8ba4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_m-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_m(mask,op1,shift,32);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_m(mask,op1,shift,32);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_m(mask,op1,shift,32);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_m(mask,op1,shift,32);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_m(mask,op1,shift,32);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_m(mask,op1,shift,32);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_m(mask,op1,shift,32);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_m(mask,op1,shift,32);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_m(mask,op1,shift,32);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_m(mask,op1,shift,32);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_m(mask,op1,shift,32);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_m(mask,op1,shift,32);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_m(mask,op1,shift,32);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_m(mask,op1,shift,32);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_m(mask,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_mu-1.c
new file mode 100644
index 0000000..d676f0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_mu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_mu-2.c
new file mode 100644
index 0000000..cd21ce4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_mu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_mu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_mu-3.c
new file mode 100644
index 0000000..0b6dc0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_mu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_mu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tu-1.c
new file mode 100644
index 0000000..881ed9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_tu(merge,op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_tu(merge,op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_tu(merge,op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_tu(vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_tu(merge,op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_tu(vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_tu(merge,op1,shift,vl);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_tu(vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_tu(merge,op1,shift,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_tu(merge,op1,shift,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_tu(merge,op1,shift,vl);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_tu(vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_tu(merge,op1,shift,vl);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_tu(vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_tu(merge,op1,shift,vl);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_tu(vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_tu(merge,op1,shift,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_tu(merge,op1,shift,vl);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_tu(vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_tu(merge,op1,shift,vl);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_tu(vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_tu(merge,op1,shift,vl);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_tu(vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_tu(merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tu-2.c
new file mode 100644
index 0000000..9f14838
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_tu(merge,op1,shift,31);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_tu(merge,op1,shift,31);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_tu(merge,op1,shift,31);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_tu(vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_tu(merge,op1,shift,31);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_tu(vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_tu(merge,op1,shift,31);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_tu(vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_tu(merge,op1,shift,31);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_tu(merge,op1,shift,31);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_tu(merge,op1,shift,31);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_tu(vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_tu(merge,op1,shift,31);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_tu(vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_tu(merge,op1,shift,31);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_tu(vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_tu(merge,op1,shift,31);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_tu(merge,op1,shift,31);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_tu(vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_tu(merge,op1,shift,31);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_tu(vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_tu(merge,op1,shift,31);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_tu(vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_tu(merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tu-3.c
new file mode 100644
index 0000000..391e90c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_tu(merge,op1,shift,32);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_tu(merge,op1,shift,32);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_tu(merge,op1,shift,32);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_tu(vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_tu(merge,op1,shift,32);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_tu(vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_tu(merge,op1,shift,32);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_tu(vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_tu(merge,op1,shift,32);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_tu(merge,op1,shift,32);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_tu(merge,op1,shift,32);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_tu(vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_tu(merge,op1,shift,32);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_tu(vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_tu(merge,op1,shift,32);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_tu(vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_tu(merge,op1,shift,32);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_tu(merge,op1,shift,32);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_tu(vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_tu(merge,op1,shift,32);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_tu(vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_tu(merge,op1,shift,32);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_tu(vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_tu(merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tum-1.c
new file mode 100644
index 0000000..7db95c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tum-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tum-2.c
new file mode 100644
index 0000000..ebf44ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tum-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_tum(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tum-3.c
new file mode 100644
index 0000000..a8a802f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tum-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_tum(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tumu-1.c
new file mode 100644
index 0000000..8fca479
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tumu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tumu-2.c
new file mode 100644
index 0000000..7782b13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tumu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tumu-3.c
new file mode 100644
index 0000000..804bcb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tumu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf8_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u8m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u16m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wv_u32m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx-1.c
new file mode 100644
index 0000000..5fb9441
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8(vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8(op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4(vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4(op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2(vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2(op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1(vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1(op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2(vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2(op1,shift,vl);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4(vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4(op1,shift,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4(vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4(op1,shift,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2(vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2(op1,shift,vl);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1(vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1(op1,shift,vl);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2(vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2(op1,shift,vl);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4(vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4(op1,shift,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2(vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2(op1,shift,vl);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1(vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1(op1,shift,vl);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2(vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2(op1,shift,vl);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4(vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4(op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx-2.c
new file mode 100644
index 0000000..30c40be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8(vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8(op1,shift,31);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4(vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4(op1,shift,31);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2(vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2(op1,shift,31);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1(vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1(op1,shift,31);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2(vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2(op1,shift,31);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4(vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4(op1,shift,31);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4(vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4(op1,shift,31);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2(vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2(op1,shift,31);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1(vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1(op1,shift,31);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2(vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2(op1,shift,31);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4(vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4(op1,shift,31);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2(vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2(op1,shift,31);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1(vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1(op1,shift,31);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2(vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2(op1,shift,31);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4(vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4(op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx-3.c
new file mode 100644
index 0000000..e921daba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8(vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8(op1,shift,32);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4(vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4(op1,shift,32);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2(vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2(op1,shift,32);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1(vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1(op1,shift,32);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2(vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2(op1,shift,32);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4(vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4(op1,shift,32);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4(vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4(op1,shift,32);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2(vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2(op1,shift,32);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1(vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1(op1,shift,32);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2(vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2(op1,shift,32);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4(vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4(op1,shift,32);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2(vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2(op1,shift,32);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1(vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1(op1,shift,32);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2(vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2(op1,shift,32);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4(vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4(op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_m-1.c
new file mode 100644
index 0000000..f2b08ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_m-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_m(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_m(mask,op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_m(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_m(mask,op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_m(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_m(mask,op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_m(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_m(mask,op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_m(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_m(mask,op1,shift,vl);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_m(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_m(mask,op1,shift,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_m(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_m(mask,op1,shift,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_m(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_m(mask,op1,shift,vl);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_m(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_m(mask,op1,shift,vl);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_m(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_m(mask,op1,shift,vl);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_m(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_m(mask,op1,shift,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_m(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_m(mask,op1,shift,vl);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_m(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_m(mask,op1,shift,vl);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_m(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_m(mask,op1,shift,vl);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_m(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_m(mask,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_m-2.c
new file mode 100644
index 0000000..2965845
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_m-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_m(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_m(mask,op1,shift,31);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_m(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_m(mask,op1,shift,31);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_m(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_m(mask,op1,shift,31);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_m(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_m(mask,op1,shift,31);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_m(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_m(mask,op1,shift,31);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_m(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_m(mask,op1,shift,31);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_m(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_m(mask,op1,shift,31);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_m(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_m(mask,op1,shift,31);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_m(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_m(mask,op1,shift,31);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_m(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_m(mask,op1,shift,31);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_m(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_m(mask,op1,shift,31);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_m(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_m(mask,op1,shift,31);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_m(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_m(mask,op1,shift,31);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_m(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_m(mask,op1,shift,31);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_m(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_m(mask,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_m-3.c
new file mode 100644
index 0000000..9c471cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_m-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_m(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_m(mask,op1,shift,32);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_m(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_m(mask,op1,shift,32);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_m(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_m(mask,op1,shift,32);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_m(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_m(mask,op1,shift,32);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_m(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_m(mask,op1,shift,32);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_m(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_m(mask,op1,shift,32);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_m(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_m(mask,op1,shift,32);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_m(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_m(mask,op1,shift,32);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_m(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_m(mask,op1,shift,32);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_m(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_m(mask,op1,shift,32);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_m(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_m(mask,op1,shift,32);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_m(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_m(mask,op1,shift,32);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_m(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_m(mask,op1,shift,32);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_m(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_m(mask,op1,shift,32);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_m(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_m(mask,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_mu-1.c
new file mode 100644
index 0000000..e86b729
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_mu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_mu-2.c
new file mode 100644
index 0000000..75bb4af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_mu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_mu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_mu-3.c
new file mode 100644
index 0000000..c28b0ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_mu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_mu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tu-1.c
new file mode 100644
index 0000000..64dc978
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_tu(merge,op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_tu(merge,op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_tu(merge,op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_tu(vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_tu(merge,op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_tu(vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_tu(merge,op1,shift,vl);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_tu(vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_tu(merge,op1,shift,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_tu(merge,op1,shift,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_tu(merge,op1,shift,vl);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_tu(vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_tu(merge,op1,shift,vl);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_tu(vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_tu(merge,op1,shift,vl);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_tu(vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_tu(merge,op1,shift,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_tu(merge,op1,shift,vl);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_tu(vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_tu(merge,op1,shift,vl);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_tu(vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_tu(merge,op1,shift,vl);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_tu(vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_tu(merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tu-2.c
new file mode 100644
index 0000000..6c86d8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_tu(merge,op1,shift,31);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_tu(merge,op1,shift,31);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_tu(merge,op1,shift,31);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_tu(vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_tu(merge,op1,shift,31);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_tu(vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_tu(merge,op1,shift,31);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_tu(vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_tu(merge,op1,shift,31);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_tu(merge,op1,shift,31);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_tu(merge,op1,shift,31);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_tu(vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_tu(merge,op1,shift,31);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_tu(vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_tu(merge,op1,shift,31);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_tu(vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_tu(merge,op1,shift,31);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_tu(merge,op1,shift,31);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_tu(vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_tu(merge,op1,shift,31);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_tu(vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_tu(merge,op1,shift,31);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_tu(vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_tu(merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tu-3.c
new file mode 100644
index 0000000..4d961c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_tu(merge,op1,shift,32);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_tu(merge,op1,shift,32);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_tu(merge,op1,shift,32);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_tu(vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_tu(merge,op1,shift,32);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_tu(vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_tu(merge,op1,shift,32);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_tu(vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_tu(merge,op1,shift,32);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_tu(merge,op1,shift,32);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_tu(merge,op1,shift,32);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_tu(vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_tu(merge,op1,shift,32);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_tu(vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_tu(merge,op1,shift,32);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_tu(vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_tu(merge,op1,shift,32);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_tu(merge,op1,shift,32);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_tu(vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_tu(merge,op1,shift,32);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_tu(vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_tu(merge,op1,shift,32);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_tu(vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_tu(merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tum-1.c
new file mode 100644
index 0000000..f87a157
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tum-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tum-2.c
new file mode 100644
index 0000000..310ae91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tum-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_tum(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tum-3.c
new file mode 100644
index 0000000..a92d31a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tum-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_tum(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tumu-1.c
new file mode 100644
index 0000000..ee194c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tumu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tumu-2.c
new file mode 100644
index 0000000..23d58a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tumu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tumu-3.c
new file mode 100644
index 0000000..675933e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tumu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vnclipu_wx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf8_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint8mf4_t test___riscv_vnclipu_wx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint8mf2_t test___riscv_vnclipu_wx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint8m1_t test___riscv_vnclipu_wx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint8m2_t test___riscv_vnclipu_wx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint8m4_t test___riscv_vnclipu_wx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u8m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint16mf4_t test___riscv_vnclipu_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint16mf2_t test___riscv_vnclipu_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint16m1_t test___riscv_vnclipu_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint16m2_t test___riscv_vnclipu_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint16m4_t test___riscv_vnclipu_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u16m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint32mf2_t test___riscv_vnclipu_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint32m1_t test___riscv_vnclipu_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint32m2_t test___riscv_vnclipu_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vuint32m4_t test___riscv_vnclipu_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnclipu_wx_u32m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */