diff options
author | Steve Ellcey <sje@cup.hp.com> | 2010-08-04 18:32:37 +0000 |
---|---|---|
committer | Steve Ellcey <sje@gcc.gnu.org> | 2010-08-04 18:32:37 +0000 |
commit | 339746734abcaef4a7ff871efdd0c2b02ffa3afc (patch) | |
tree | aeb803c62cd134d45b19cbdee16678cff31e4443 /gcc | |
parent | 3b0c690efc298363b4043746b058852fdafc5799 (diff) | |
download | gcc-339746734abcaef4a7ff871efdd0c2b02ffa3afc.zip gcc-339746734abcaef4a7ff871efdd0c2b02ffa3afc.tar.gz gcc-339746734abcaef4a7ff871efdd0c2b02ffa3afc.tar.bz2 |
re PR target/44583 (c-c++-common/torture/complex-sign-add.c fails for signed zeros)
2010-07-29 Steve Ellcey <sje@cup.hp.com>
PR target/44583
* config/ia64/constraints.md (Z): New.
* config/ia64/predicates.md (fr_reg_or_signed_fp01_operand): New.
(xfreg_or_signed_fp01_operand): New.
* config/ia64/ia64.md (addsf3): Replace fr_reg_or_fp01_operand
with fr_reg_or_signed_fp01_operand and constraint G with Z.
(subsf3): Ditto.
(*maddsf4): Ditto.
(*msubsf4): Ditto.
(adddf3): Ditto.
(adddf3_trunc): Ditto.
(subdf3): Ditto.
(*subdf3_trunc): Ditto.
(*madddf4): Ditto.
(*madddf4_trunc): Ditto.
(*msubdf4): Ditto.
(*msubdf4_trunc): Ditto.
(addxf3): Replace xfreg_or_fp01_operand with
xfreg_or_signed_fp01_operand and constraint G with Z.
(*addxf3_truncsf): Ditto.
(*addxf3_truncdf): Ditto.
(subxf3): Ditto.
(*subxf3_truncsf): Ditto.
(*subxf3_truncdf): Ditto.
(*maddxf4): Ditto.
(*maddxf4_truncsf): Ditto.
(*maddxf4_truncdf): Ditto.
(*msubxf4): Ditto.
(*msubxf4_truncsf): Ditto.
(*msubxf4_truncdf): Ditto.
From-SVN: r162869
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 33 | ||||
-rw-r--r-- | gcc/config/ia64/constraints.md | 7 | ||||
-rw-r--r-- | gcc/config/ia64/ia64.md | 60 | ||||
-rw-r--r-- | gcc/config/ia64/predicates.md | 13 |
4 files changed, 83 insertions, 30 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 23f0d88..0fc6486 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,36 @@ +2010-08-04 Steve Ellcey <sje@cup.hp.com> + + PR target/44583 + * config/ia64/constraints.md (Z): New. + * config/ia64/predicates.md (fr_reg_or_signed_fp01_operand): New. + (xfreg_or_signed_fp01_operand): New. + * config/ia64/ia64.md (addsf3): Replace fr_reg_or_fp01_operand + with fr_reg_or_signed_fp01_operand and constraint G with Z. + (subsf3): Ditto. + (*maddsf4): Ditto. + (*msubsf4): Ditto. + (adddf3): Ditto. + (adddf3_trunc): Ditto. + (subdf3): Ditto. + (*subdf3_trunc): Ditto. + (*madddf4): Ditto. + (*madddf4_trunc): Ditto. + (*msubdf4): Ditto. + (*msubdf4_trunc): Ditto. + (addxf3): Replace xfreg_or_fp01_operand with + xfreg_or_signed_fp01_operand and constraint G with Z. + (*addxf3_truncsf): Ditto. + (*addxf3_truncdf): Ditto. + (subxf3): Ditto. + (*subxf3_truncsf): Ditto. + (*subxf3_truncdf): Ditto. + (*maddxf4): Ditto. + (*maddxf4_truncsf): Ditto. + (*maddxf4_truncdf): Ditto. + (*msubxf4): Ditto. + (*msubxf4_truncsf): Ditto. + (*msubxf4_truncdf): Ditto. + 2010-08-04 Richard Guenther <rguenther@suse.de> * alias.c (rtx_refs_may_alias_p): Do not resort to TBAA diff --git a/gcc/config/ia64/constraints.md b/gcc/config/ia64/constraints.md index 5d11913..aeb846e 100644 --- a/gcc/config/ia64/constraints.md +++ b/gcc/config/ia64/constraints.md @@ -95,6 +95,13 @@ (and (match_code "const_double") (match_test "op == CONST0_RTX (mode) || op == CONST1_RTX (mode)"))) +(define_constraint "Z" + "1.0 or (0.0 and !flag_signed_zeros)" + (and (match_code "const_double") + (ior (match_test "op == CONST1_RTX (mode)") + (and (match_test "op == CONST0_RTX (mode)") + (match_test "!flag_signed_zeros"))))) + (define_constraint "H" "0.0" (and (match_code "const_double") diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index 26c8847..aa26248 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -2663,8 +2663,8 @@ (define_insn "addsf3" [(set (match_operand:SF 0 "fr_register_operand" "=f") - (plus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") - (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] + (plus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "%fG") + (match_operand:SF 2 "fr_reg_or_signed_fp01_operand" "fZ")))] "" "fadd.s %0 = %F1, %F2" [(set_attr "itanium_class" "fmac")]) @@ -2672,7 +2672,7 @@ (define_insn "subsf3" [(set (match_operand:SF 0 "fr_register_operand" "=f") (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") - (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] + (match_operand:SF 2 "fr_reg_or_signed_fp01_operand" "fZ")))] "" "fsub.s %0 = %F1, %F2" [(set_attr "itanium_class" "fmac")]) @@ -2744,7 +2744,7 @@ [(set (match_operand:SF 0 "fr_register_operand" "=f") (plus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")) - (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] + (match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] "TARGET_FUSED_MADD" "fma.s %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) @@ -2753,7 +2753,7 @@ [(set (match_operand:SF 0 "fr_register_operand" "=f") (minus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")) - (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] + (match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] "TARGET_FUSED_MADD" "fms.s %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) @@ -2783,8 +2783,8 @@ (define_insn "adddf3" [(set (match_operand:DF 0 "fr_register_operand" "=f") - (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") - (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] + (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "%fG") + (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ")))] "" "fadd.d %0 = %F1, %F2" [(set_attr "itanium_class" "fmac")]) @@ -2792,8 +2792,8 @@ (define_insn "*adddf3_trunc" [(set (match_operand:SF 0 "fr_register_operand" "=f") (float_truncate:SF - (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") - (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] + (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "%fG") + (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ"))))] "" "fadd.s %0 = %F1, %F2" [(set_attr "itanium_class" "fmac")]) @@ -2801,7 +2801,7 @@ (define_insn "subdf3" [(set (match_operand:DF 0 "fr_register_operand" "=f") (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") - (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] + (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ")))] "" "fsub.d %0 = %F1, %F2" [(set_attr "itanium_class" "fmac")]) @@ -2810,7 +2810,7 @@ [(set (match_operand:SF 0 "fr_register_operand" "=f") (float_truncate:SF (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") - (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] + (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ"))))] "" "fsub.s %0 = %F1, %F2" [(set_attr "itanium_class" "fmac")]) @@ -2891,7 +2891,7 @@ [(set (match_operand:DF 0 "fr_register_operand" "=f") (plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) - (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] + (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] "TARGET_FUSED_MADD" "fma.d %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) @@ -2901,7 +2901,7 @@ (float_truncate:SF (plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) - (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] + (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))] "TARGET_FUSED_MADD" "fma.s %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) @@ -2910,7 +2910,7 @@ [(set (match_operand:DF 0 "fr_register_operand" "=f") (minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) - (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] + (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] "TARGET_FUSED_MADD" "fms.d %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) @@ -2920,7 +2920,7 @@ (float_truncate:SF (minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) - (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] + (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))] "TARGET_FUSED_MADD" "fms.s %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) @@ -2969,8 +2969,8 @@ (define_insn "addxf3" [(set (match_operand:XF 0 "fr_register_operand" "=f") - (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] + (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG") + (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ")))] "" "fadd %0 = %F1, %F2" [(set_attr "itanium_class" "fmac")]) @@ -2978,8 +2978,8 @@ (define_insn "*addxf3_truncsf" [(set (match_operand:SF 0 "fr_register_operand" "=f") (float_truncate:SF - (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] + (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG") + (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))] "" "fadd.s %0 = %F1, %F2" [(set_attr "itanium_class" "fmac")]) @@ -2987,8 +2987,8 @@ (define_insn "*addxf3_truncdf" [(set (match_operand:DF 0 "fr_register_operand" "=f") (float_truncate:DF - (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] + (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG") + (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))] "" "fadd.d %0 = %F1, %F2" [(set_attr "itanium_class" "fmac")]) @@ -2996,7 +2996,7 @@ (define_insn "subxf3" [(set (match_operand:XF 0 "fr_register_operand" "=f") (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] + (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ")))] "" "fsub %0 = %F1, %F2" [(set_attr "itanium_class" "fmac")]) @@ -3005,7 +3005,7 @@ [(set (match_operand:SF 0 "fr_register_operand" "=f") (float_truncate:SF (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] + (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))] "" "fsub.s %0 = %F1, %F2" [(set_attr "itanium_class" "fmac")]) @@ -3014,7 +3014,7 @@ [(set (match_operand:DF 0 "fr_register_operand" "=f") (float_truncate:DF (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") - (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] + (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))] "" "fsub.d %0 = %F1, %F2" [(set_attr "itanium_class" "fmac")]) @@ -3104,7 +3104,7 @@ [(set (match_operand:XF 0 "fr_register_operand" "=f") (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) - (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] + (match_operand:XF 3 "xfreg_or_signed_fp01_operand" "fZ")))] "TARGET_FUSED_MADD" "fma %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) @@ -3114,7 +3114,7 @@ (float_truncate:SF (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) - (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] + (match_operand:XF 3 "xfreg_or_signed_fp01_operand" "fZ"))))] "TARGET_FUSED_MADD" "fma.s %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) @@ -3124,7 +3124,7 @@ (float_truncate:DF (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) - (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] + (match_operand:XF 3 "xfreg_or_signed_fp01_operand" "fZ"))))] "TARGET_FUSED_MADD" "fma.d %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) @@ -3133,7 +3133,7 @@ [(set (match_operand:XF 0 "fr_register_operand" "=f") (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) - (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] + (match_operand:XF 3 "xfreg_or_signed_fp01_operand" "fZ")))] "TARGET_FUSED_MADD" "fms %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) @@ -3143,7 +3143,7 @@ (float_truncate:SF (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) - (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] + (match_operand:XF 3 "xfreg_or_signed_fp01_operand" "fZ"))))] "TARGET_FUSED_MADD" "fms.s %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) @@ -3153,7 +3153,7 @@ (float_truncate:DF (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) - (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] + (match_operand:XF 3 "xfreg_or_signed_fp01_operand" "fZ"))))] "TARGET_FUSED_MADD" "fms.d %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md index 2d0af6f..af24827 100644 --- a/gcc/config/ia64/predicates.md +++ b/gcc/config/ia64/predicates.md @@ -542,6 +542,19 @@ (and (match_operand 0 "fr_reg_or_fp01_operand") (not (match_code "subreg")))) +;; Like fr_reg_or_fp01_operand, but don't allow 0 if flag_signed_zero is set. +;; Using f0 as the second arg to fadd or fsub, or as the third arg to fma or +;; fms can cause a zero result to have the wrong sign. +(define_predicate "fr_reg_or_signed_fp01_operand" + (ior (match_operand 0 "fr_register_operand") + (and (match_code "const_double") + (match_test "satisfies_constraint_Z (op)")))) + +;; Like fr_reg_or_signed_fp01_operand, but don't allow any SUBREGs. +(define_predicate "xfreg_or_signed_fp01_operand" + (and (match_operand 0 "fr_reg_or_signed_fp01_operand") + (not (match_code "subreg")))) + ;; True if OP is a constant zero, or a register. (define_predicate "fr_reg_or_0_operand" (ior (match_operand 0 "fr_register_operand") |