sparc.c: Remove all references to TARGET_EPILOGUE.

        * config/sparc/sparc.c: Remove all references to TARGET_EPILOGUE.
        (sparc_emitting_epilogue): New.
        (leaf_label, output_return, sparc_return_peephole_ok): Remove.
        * config/sparc/sparc-protos.h: Update.
        * config/sparc/sparc.h (MASK_EPILOGUE, TARGET_EPILOGUE): Remove.
        (TARGET_SWITCHES): Update.
        * config/sparc/sparc.md (return): Remove.
        (return_*): Use sparc_emitting_epilogue, not !TARGET_EPILOGUE.
        * config/sparc/freebsd.h, config/sparc/linux64.h, config/sparc/lite.h,
        config/sparc/liteelf.h, config/sparc/netbsd-elf.h,
        config/sparc/sol2-sld-64.h, config/sparc/sol2.h,
        config/sparc/sp64-aout.h, config/sparc/sp64-elf.h,
        config/sparc/sp86x-aout.h, config/sparc/sp86x-elf.h,
        config/sparc/splet.h, config/sparc/vxsparc64.h (TARGET_DEFAULT):
        Remove MASK_EPILOGUE.
        * doc/invoke.texi: Update.

From-SVN: r51626

19 files changed, 148 insertions, 305 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index be40f66..f11319c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,22 @@
+2002-03-30  Richard Henderson  <rth@redhat.com>
+
+	* config/sparc/sparc.c: Remove all references to TARGET_EPILOGUE.
+	(sparc_emitting_epilogue): New.
+	(leaf_label, output_return, sparc_return_peephole_ok): Remove.
+	* config/sparc/sparc-protos.h: Update.
+	* config/sparc/sparc.h (MASK_EPILOGUE, TARGET_EPILOGUE): Remove.
+	(TARGET_SWITCHES): Update.
+	* config/sparc/sparc.md (return): Remove.
+	(return_*): Use sparc_emitting_epilogue, not !TARGET_EPILOGUE.
+	* config/sparc/freebsd.h, config/sparc/linux64.h, config/sparc/lite.h,
+	config/sparc/liteelf.h, config/sparc/netbsd-elf.h,
+	config/sparc/sol2-sld-64.h, config/sparc/sol2.h,
+	config/sparc/sp64-aout.h, config/sparc/sp64-elf.h,
+	config/sparc/sp86x-aout.h, config/sparc/sp86x-elf.h,
+	config/sparc/splet.h, config/sparc/vxsparc64.h (TARGET_DEFAULT):
+	Remove MASK_EPILOGUE.
+	* doc/invoke.texi: Update.
+
 2002-03-30  Daniel Berlin  <dan@dberlin.org>
 
 	* dwarf2out.c (dwarf2out_define): Remove start_source_file call,
diff --git a/gcc/config/sparc/freebsd.h b/gcc/config/sparc/freebsd.h
index 7654b7a..9017839 100644
--- a/gcc/config/sparc/freebsd.h
+++ b/gcc/config/sparc/freebsd.h
@@ -92,7 +92,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
 #undef  TARGET_DEFAULT
 #define TARGET_DEFAULT \
   (MASK_V9 + MASK_64BIT + MASK_PTR64 /* + MASK_FASTER_STRUCTS */ \
-   + MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU \
+   + MASK_STACK_BIAS + MASK_APP_REGS + MASK_FPU \
    + MASK_LONG_DOUBLE_128 /* + MASK_HARD_QUAD */)
 
 /* The default code model.  */
diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h
index 55624fb..7c31d87 100644
--- a/gcc/config/sparc/linux64.h
+++ b/gcc/config/sparc/linux64.h
@@ -36,7 +36,7 @@ Boston, MA 02111-1307, USA.  */
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT \
   (MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \
-   + MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_LONG_DOUBLE_128)
+   + MASK_STACK_BIAS + MASK_APP_REGS + MASK_FPU + MASK_LONG_DOUBLE_128)
 #endif
 
 #undef ASM_CPU_DEFAULT_SPEC
diff --git a/gcc/config/sparc/lite.h b/gcc/config/sparc/lite.h
index f740443..95da781 100644
--- a/gcc/config/sparc/lite.h
+++ b/gcc/config/sparc/lite.h
@@ -28,7 +28,7 @@ Boston, MA 02111-1307, USA.  */
 /* Enable app-regs and epilogue options.  Do not enable the fpu.  */
 
 #undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
+#define TARGET_DEFAULT MASK_APP_REGS
 
 /* US Software GOFAST library support.  */
 #undef INIT_SUBTARGET_OPTABS
diff --git a/gcc/config/sparc/liteelf.h b/gcc/config/sparc/liteelf.h
index d7c88b5..5c93c2d 100644
--- a/gcc/config/sparc/liteelf.h
+++ b/gcc/config/sparc/liteelf.h
@@ -38,7 +38,7 @@ Boston, MA 02111-1307, USA.  */
 /* Enable app-regs and epilogue options.  Do not enable the fpu.  */
 
 #undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
+#define TARGET_DEFAULT MASK_APP_REGS
 
 /* US Software GOFAST library support.  */
 #undef INIT_SUBTARGET_OPTABS
diff --git a/gcc/config/sparc/netbsd-elf.h b/gcc/config/sparc/netbsd-elf.h
index f454b96..9ed9b51 100644
--- a/gcc/config/sparc/netbsd-elf.h
+++ b/gcc/config/sparc/netbsd-elf.h
@@ -137,8 +137,7 @@ Boston, MA 02111-1307, USA.  */
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT \
   (MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \
- + MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU \
- + MASK_LONG_DOUBLE_128)
+   + MASK_STACK_BIAS + MASK_APP_REGS + MASK_FPU + MASK_LONG_DOUBLE_128)
 
 #undef SPARC_DEFAULT_CMODEL
 #define SPARC_DEFAULT_CMODEL CM_MEDANY
diff --git a/gcc/config/sparc/sol2-sld-64.h b/gcc/config/sparc/sol2-sld-64.h
index 73b0822..2a8eafc 100644
--- a/gcc/config/sparc/sol2-sld-64.h
+++ b/gcc/config/sparc/sol2-sld-64.h
@@ -27,7 +27,7 @@
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT \
   (MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ + \
-   MASK_STACK_BIAS + MASK_EPILOGUE + MASK_FPU + MASK_LONG_DOUBLE_128)
+   MASK_STACK_BIAS + MASK_FPU + MASK_LONG_DOUBLE_128)
 #endif
 
 /* The default code model.  */
diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h
index 64e54b7..3541cac 100644
--- a/gcc/config/sparc/sol2.h
+++ b/gcc/config/sparc/sol2.h
@@ -237,7 +237,7 @@ Boston, MA 02111-1307, USA.  */
 /* Solaris allows 64 bit out and global registers in 32 bit mode.
    sparc_override_options will disable V8+ if not generating V9 code.  */
 #undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_EPILOGUE + MASK_FPU + MASK_V8PLUS + MASK_LONG_DOUBLE_128)
+#define TARGET_DEFAULT (MASK_FPU + MASK_V8PLUS + MASK_LONG_DOUBLE_128)
 
 /*
  * Attempt to turn on access permissions for the stack.
diff --git a/gcc/config/sparc/sp64-aout.h b/gcc/config/sparc/sp64-aout.h
index 669adc3..1af9dea 100644
--- a/gcc/config/sparc/sp64-aout.h
+++ b/gcc/config/sparc/sp64-aout.h
@@ -26,7 +26,7 @@ Boston, MA 02111-1307, USA.  */
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT \
   (MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
-   + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_STACK_BIAS)
+   + MASK_APP_REGS + MASK_FPU + MASK_STACK_BIAS)
 
 /* The only code model supported is Medium/Low.  */
 #undef SPARC_DEFAULT_CMODEL
diff --git a/gcc/config/sparc/sp64-elf.h b/gcc/config/sparc/sp64-elf.h
index 3bd2a53..2574c1e 100644
--- a/gcc/config/sparc/sp64-elf.h
+++ b/gcc/config/sparc/sp64-elf.h
@@ -33,7 +33,7 @@ Boston, MA 02111-1307, USA.  */
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT \
 (MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
- + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_STACK_BIAS + MASK_LONG_DOUBLE_128)
+ + MASK_APP_REGS + MASK_FPU + MASK_STACK_BIAS + MASK_LONG_DOUBLE_128)
 
 #undef SPARC_DEFAULT_CMODEL
 #define SPARC_DEFAULT_CMODEL CM_EMBMEDANY
diff --git a/gcc/config/sparc/sp86x-aout.h b/gcc/config/sparc/sp86x-aout.h
index ed31925..74607d3 100644
--- a/gcc/config/sparc/sp86x-aout.h
+++ b/gcc/config/sparc/sp86x-aout.h
@@ -28,7 +28,7 @@ Boston, MA 02111-1307, USA.  */
 /* Enable app-regs and epilogue options.  Do not enable the fpu.  */
 
 #undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
+#define TARGET_DEFAULT MASK_APP_REGS
 
 #undef ASM_SPEC
 #define ASM_SPEC "%{v:-v} %{mlittle-endian-data:--little-endian-data} %(asm_cpu)"
diff --git a/gcc/config/sparc/sp86x-elf.h b/gcc/config/sparc/sp86x-elf.h
index 40ecd55..42239a9 100644
--- a/gcc/config/sparc/sp86x-elf.h
+++ b/gcc/config/sparc/sp86x-elf.h
@@ -38,7 +38,7 @@ Boston, MA 02111-1307, USA.  */
 /* Enable app-regs and epilogue options.  Do not enable the fpu.  */
 
 #undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
+#define TARGET_DEFAULT MASK_APP_REGS
 
 #undef ASM_SPEC
 #define ASM_SPEC "%{v:-V} %{mlittle-endian-data:--little-endian-data} %(asm_cpu)"
diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h
index 8c5c7ff..0f3cef4 100644
--- a/gcc/config/sparc/sparc-protos.h
+++ b/gcc/config/sparc/sparc-protos.h
@@ -24,6 +24,8 @@ Boston, MA 02111-1307, USA.  */
 #ifndef __SPARC_PROTOS_H__
 #define __SPARC_PROTOS_H__
 
+extern bool sparc_emitting_epilogue;
+
 #ifdef TREE_CODE
 extern struct rtx_def *function_value PARAMS ((tree, enum machine_mode, int));
 extern void function_arg_advance PARAMS ((CUMULATIVE_ARGS *,
@@ -84,7 +86,6 @@ extern void sparc_emit_set_symbolic_const64 PARAMS ((rtx, rtx, rtx));
 extern int sparc_splitdi_legitimate PARAMS ((rtx, rtx));
 extern int sparc_absnegfloat_split_legitimate PARAMS ((rtx, rtx));
 extern char *output_cbranch PARAMS ((rtx, rtx, int, int, int, int, rtx));
-extern const char *output_return PARAMS ((rtx *));
 extern const char *output_sibcall PARAMS ((rtx, rtx));
 extern char *output_v9branch PARAMS ((rtx, rtx, int, int, int, int, int,
 				      rtx));
@@ -115,7 +116,6 @@ extern char *sparc_v8plus_shift PARAMS ((rtx *, rtx, const char *));
 /* Function used for V8+ code generation.  Returns 1 if the high
    32 bits of REG are 0 before INSN.  */   
 extern int sparc_check_64 PARAMS ((rtx, rtx));
-extern int sparc_return_peephole_ok PARAMS ((rtx, rtx));
 extern rtx gen_df_reg PARAMS ((rtx, int));
 #endif /* RTX_CODE */
 
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index ec53404..f2b9188 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -68,18 +68,17 @@ Boston, MA 02111-1307, USA.  */
 static int apparent_fsize;
 static int actual_fsize;
 
-/* Number of live general or floating point registers needed to be saved
-   (as 4-byte quantities).  This is only done if TARGET_EPILOGUE.  */
+/* Number of live general or floating point registers needed to be
+   saved (as 4-byte quantities).  */
 static int num_gfregs;
 
 /* Save the operands last given to a compare for use when we
    generate a scc or bcc insn.  */
-
 rtx sparc_compare_op0, sparc_compare_op1;
 
-/* We may need an epilogue if we spill too many registers.
-   If this is non-zero, then we branch here for the epilogue.  */
-static rtx leaf_label;
+/* Coordinate with the md file wrt special insns created by
+   sparc_nonflat_function_epilogue.  */
+bool sparc_emitting_epilogue;
 
 #ifdef LEAF_REGISTERS
 
@@ -3392,31 +3391,28 @@ compute_frame_size (size, leaf_function)
   int outgoing_args_size = (current_function_outgoing_args_size
 			    + REG_PARM_STACK_SPACE (current_function_decl));
 
-  if (TARGET_EPILOGUE)
-    {
-      /* N_REGS is the number of 4-byte regs saved thus far.  This applies
-	 even to v9 int regs to be consistent with save_regs/restore_regs.  */
-
-      if (TARGET_ARCH64)
-	{
-	  for (i = 0; i < 8; i++)
-	    if (regs_ever_live[i] && ! call_used_regs[i])
-	      n_regs += 2;
-	}
-      else
-	{
-	  for (i = 0; i < 8; i += 2)
-	    if ((regs_ever_live[i] && ! call_used_regs[i])
-		|| (regs_ever_live[i+1] && ! call_used_regs[i+1]))
-	      n_regs += 2;
-	}
+  /* N_REGS is the number of 4-byte regs saved thus far.  This applies
+     even to v9 int regs to be consistent with save_regs/restore_regs.  */
 
-      for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
+  if (TARGET_ARCH64)
+    {
+      for (i = 0; i < 8; i++)
+	if (regs_ever_live[i] && ! call_used_regs[i])
+	  n_regs += 2;
+    }
+  else
+    {
+      for (i = 0; i < 8; i += 2)
 	if ((regs_ever_live[i] && ! call_used_regs[i])
 	    || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
 	  n_regs += 2;
     }
 
+  for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
+    if ((regs_ever_live[i] && ! call_used_regs[i])
+	|| (regs_ever_live[i+1] && ! call_used_regs[i+1]))
+      n_regs += 2;
+
   /* Set up values for use in `function_epilogue'.  */
   num_gfregs = n_regs;
 
@@ -3640,24 +3636,9 @@ sparc_nonflat_function_prologue (file, size, leaf_function)
 	  base = frame_base_name;
 	}
 
-      n_regs = 0;
-      if (TARGET_EPILOGUE && ! leaf_function)
-	/* ??? Originally saved regs 0-15 here.  */
-	n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
-      else if (leaf_function)
-	/* ??? Originally saved regs 0-31 here.  */
-	n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
-      if (TARGET_EPILOGUE)
-	save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
-		   real_offset);
-    }
-
-  leaf_label = 0;
-  if (leaf_function && actual_fsize != 0)
-    {
-      /* warning ("leaf procedure with frame size %d", actual_fsize); */
-      if (! TARGET_EPILOGUE)
-	leaf_label = gen_label_rtx ();
+      n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
+      save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
+		 real_offset);
     }
 }
 
@@ -3684,15 +3665,8 @@ output_restore_regs (file, leaf_function)
       base = frame_base_name;
     }
 
-  n_regs = 0;
-  if (TARGET_EPILOGUE && ! leaf_function)
-    /* ??? Originally saved regs 0-15 here.  */
-    n_regs = restore_regs (file, 0, 8, base, offset, 0);
-  else if (leaf_function)
-    /* ??? Originally saved regs 0-31 here.  */
-    n_regs = restore_regs (file, 0, 8, base, offset, 0);
-  if (TARGET_EPILOGUE)
-    restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
+  n_regs = restore_regs (file, 0, 8, base, offset, 0);
+  restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
 }
 
 /* This function generates the assembly code for function exit,
@@ -3725,12 +3699,6 @@ sparc_nonflat_function_epilogue (file, size, leaf_function)
 {
   const char *ret;
 
-  if (leaf_label)
-    {
-      emit_label_after (leaf_label, get_last_insn ());
-      final_scan_insn (get_last_insn (), file, 0, 0, 1);
-    }
-
   if (current_function_epilogue_delay_list == 0)
     {
       /* If code does not drop into the epilogue, we need
@@ -3751,95 +3719,93 @@ sparc_nonflat_function_epilogue (file, size, leaf_function)
   else
     ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
 
-  if (TARGET_EPILOGUE || leaf_label)
+  if (! leaf_function)
     {
-      int old_target_epilogue = TARGET_EPILOGUE;
-      target_flags &= ~old_target_epilogue;
+      if (current_function_calls_eh_return)
+	{
+	  if (current_function_epilogue_delay_list)
+	    abort ();
+	  if (SKIP_CALLERS_UNIMP_P)
+	    abort ();
 
-      if (! leaf_function)
+	  fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
+	}
+      /* If we wound up with things in our delay slot, flush them here.  */
+      else if (current_function_epilogue_delay_list)
 	{
-	  if (current_function_calls_eh_return)
-	    {
-	      if (current_function_epilogue_delay_list)
-		abort ();
-	      if (SKIP_CALLERS_UNIMP_P)
-		abort ();
+	  rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
 
-	      fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
+	  if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
+	    {
+	      epilogue_renumber (&delay, 0);
+	      fputs (SKIP_CALLERS_UNIMP_P
+		     ? "\treturn\t%i7+12\n"
+		     : "\treturn\t%i7+8\n", file);
+	      final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
+			       file, 1, 0, 0);
 	    }
-	  /* If we wound up with things in our delay slot, flush them here.  */
-	  else if (current_function_epilogue_delay_list)
+	  else
 	    {
-	      rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
+	      rtx insn, src;
 
-	      if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
-		{
-		  epilogue_renumber (&delay, 0);
-		  fputs (SKIP_CALLERS_UNIMP_P
-			 ? "\treturn\t%i7+12\n"
-			 : "\treturn\t%i7+8\n", file);
-		  final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), file, 1, 0, 0);
-		}
-	      else
-		{
-		  rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode),
-						   get_last_insn ());
-		  rtx src;
+	      if (GET_CODE (delay) != SET)
+		abort();
 
-		  if (GET_CODE (delay) != SET)
+	      src = SET_SRC (delay);
+	      if (GET_CODE (src) == ASHIFT)
+		{
+		  if (XEXP (src, 1) != const1_rtx)
 		    abort();
+		  SET_SRC (delay)
+		    = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
+				    XEXP (src, 0));
+		}
 
-		  src = SET_SRC (delay);
-		  if (GET_CODE (src) == ASHIFT)
-		    {
-		      if (XEXP (src, 1) != const1_rtx)
-			abort();
-		      SET_SRC (delay) = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
-						      XEXP (src, 0));
-		    }
+	      insn = gen_rtx_PARALLEL (VOIDmode,
+				       gen_rtvec (2, delay,
+						  gen_rtx_RETURN (VOIDmode)));
+	      insn = emit_jump_insn (insn);
 
-		  PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode,
-					gen_rtvec (2, delay, PATTERN (insn)));
-		  final_scan_insn (insn, file, 1, 0, 1);
-		}
+	      sparc_emitting_epilogue = true;
+	      final_scan_insn (insn, file, 1, 0, 1);
+	      sparc_emitting_epilogue = false;
 	    }
-	  else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
-	    fputs ("\treturn\t%i7+8\n\tnop\n", file);
-	  else
-	    fprintf (file, "\t%s\n\trestore\n", ret);
 	}
-      else if (current_function_calls_eh_return)
+      else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
+	fputs ("\treturn\t%i7+8\n\tnop\n", file);
+      else
+	fprintf (file, "\t%s\n\trestore\n", ret);
+    }
+  /* All of the following cases are for leaf functions.  */
+  else if (current_function_calls_eh_return)
+    abort ();
+  else if (current_function_epilogue_delay_list)
+    {
+      /* eligible_for_epilogue_delay_slot ensures that if this is a
+	 leaf function, then we will only have insn in the delay slot
+	 if the frame size is zero, thus no adjust for the stack is
+	 needed here.  */
+      if (actual_fsize != 0)
 	abort ();
-      /* All of the following cases are for leaf functions.  */
-      else if (current_function_epilogue_delay_list)
-	{
-	  /* eligible_for_epilogue_delay_slot ensures that if this is a
-	     leaf function, then we will only have insn in the delay slot
-	     if the frame size is zero, thus no adjust for the stack is
-	     needed here.  */
-	  if (actual_fsize != 0)
-	    abort ();
-	  fprintf (file, "\t%s\n", ret);
-	  final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
-			   file, 1, 0, 1);
-	}
-      /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
-	 avoid generating confusing assembly language output.  */
-      else if (actual_fsize == 0)
-	fprintf (file, "\t%s\n\tnop\n", ret);
-      else if (actual_fsize <= 4096)
-	fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
-      else if (actual_fsize <= 8192)
-	fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
-		 ret, actual_fsize - 4096);
-      else if ((actual_fsize & 0x3ff) == 0)
-	fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
-		 actual_fsize, ret);
-      else		 
-	fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
-		 actual_fsize, actual_fsize, ret);
-      target_flags |= old_target_epilogue;
+      fprintf (file, "\t%s\n", ret);
+      final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
+		       file, 1, 0, 1);
     }
+  /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
+	 avoid generating confusing assembly language output.  */
+  else if (actual_fsize == 0)
+    fprintf (file, "\t%s\n\tnop\n", ret);
+  else if (actual_fsize <= 4096)
+    fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
+  else if (actual_fsize <= 8192)
+    fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
+	     ret, actual_fsize - 4096);
+  else if ((actual_fsize & 0x3ff) == 0)
+    fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
+	     actual_fsize, ret);
+  else		 
+    fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
+	     actual_fsize, actual_fsize, ret);
 
  output_vectors:
   sparc_output_deferred_case_vectors ();
@@ -5699,87 +5665,6 @@ epilogue_renumber (where, test)
     }
   return 0;
 }
-
-/* Output assembler code to return from a function.  */
-
-const char *
-output_return (operands)
-     rtx *operands;
-{
-  rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0;
-
-  if (leaf_label)
-    {
-      operands[0] = leaf_label;
-      return "b%* %l0%(";
-    }
-  else if (current_function_uses_only_leaf_regs)
-    {
-      /* No delay slot in a leaf function.  */
-      if (delay)
-	abort ();
-
-      /* If we didn't allocate a frame pointer for the current function,
-	 the stack pointer might have been adjusted.  Output code to
-	 restore it now.  */
-
-      operands[0] = GEN_INT (actual_fsize);
-
-      /* Use sub of negated value in first two cases instead of add to
-	 allow actual_fsize == 4096.  */
-
-      if (actual_fsize <= 4096)
-	{
-	  if (SKIP_CALLERS_UNIMP_P)
-	    return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
-	  else
-	    return "retl\n\tsub\t%%sp, -%0, %%sp";
-	}
-      else if (actual_fsize <= 8192)
-	{
-	  operands[0] = GEN_INT (actual_fsize - 4096);
-	  if (SKIP_CALLERS_UNIMP_P)
-	    return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
-	  else
-	    return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
-	}
-      else if (SKIP_CALLERS_UNIMP_P)
-	{
-	  if ((actual_fsize & 0x3ff) != 0)
-	    return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
-	  else
-	    return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
-	}
-      else
-	{
-	  if ((actual_fsize & 0x3ff) != 0)
-	    return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tretl\n\tadd\t%%sp, %%g1, %%sp";
-	  else
-	    return "sethi\t%%hi(%a0), %%g1\n\tretl\n\tadd\t%%sp, %%g1, %%sp";
-	}
-    }
-  else if (TARGET_V9)
-    {
-      if (delay)
-	{
-	  epilogue_renumber (&SET_DEST (PATTERN (delay)), 0);
-	  epilogue_renumber (&SET_SRC (PATTERN (delay)), 0);
-	}
-      if (SKIP_CALLERS_UNIMP_P)
-	return "return\t%%i7+12%#";
-      else
-	return "return\t%%i7+8%#";
-    }
-  else
-    {
-      if (delay)
-	abort ();
-      if (SKIP_CALLERS_UNIMP_P)
-	return "jmp\t%%i7+12\n\trestore";
-      else
-	return "ret\n\trestore";
-    }
-}
 
 /* Leaf functions and non-leaf functions have different needs.  */
 
@@ -8593,23 +8478,6 @@ sparc_v8plus_shift (operands, insn, opcode)
   else
     return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
 }
-
-
-/* Return 1 if DEST and SRC reference only global and in registers.  */
-
-int
-sparc_return_peephole_ok (dest, src)
-     rtx dest, src;
-{
-  if (! TARGET_V9)
-    return 0;
-  if (current_function_uses_only_leaf_regs)
-    return 0;
-  if (GET_CODE (src) != CONST_INT
-      && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src)))
-    return 0;
-  return IN_OR_GLOBAL_P (dest);
-}
 
 /* Output rtl to increment the profiler label LABELNO
    for profiling a function entry.  */
@@ -8651,7 +8519,6 @@ sparc_add_gc_roots ()
 {
   ggc_add_rtx_root (&sparc_compare_op0, 1);
   ggc_add_rtx_root (&sparc_compare_op1, 1);
-  ggc_add_rtx_root (&leaf_label, 1);
   ggc_add_rtx_root (&global_offset_table, 1);
   ggc_add_rtx_root (&get_pc_symbol, 1);
   ggc_add_rtx_root (&sparc_addr_diff_list, 1);
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index fba2cc6..d488a8f 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -387,11 +387,6 @@ extern int target_flags;
 #define MASK_FPU 1
 #define TARGET_FPU (target_flags & MASK_FPU)
 
-/* Nonzero if we should use function_epilogue().  Otherwise, we
-   use fast return insns, but lose some generality.  */
-#define MASK_EPILOGUE 2
-#define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
-
 /* Nonzero if we should assume that double pointers might be unaligned.
    This can happen when linking gcc compiled code with other compilers,
    because the ABI only guarantees 4 byte alignment.  */
@@ -535,10 +530,6 @@ extern int target_flags;
     {"soft-float", -MASK_FPU,						\
      N_("Do not use hardware fp") },					\
     {"soft-float", MASK_FPU_SET,			NULL },		\
-    {"epilogue", MASK_EPILOGUE,						\
-     N_("Use function_epilogue()") },					\
-    {"no-epilogue", -MASK_EPILOGUE,					\
-     N_("Do not use function_epilogue()") }, 				\
     {"unaligned-doubles", MASK_UNALIGNED_DOUBLES,			\
      N_("Assume possible double misalignment") },			\
     {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES,			\
@@ -607,7 +598,7 @@ extern int target_flags;
 /* MASK_APP_REGS must always be the default because that's what
    FIXED_REGISTERS is set to and -ffixed- is processed before
    CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs).  */
-#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
+#define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
 
 /* This is meant to be redefined in target specific files.  */
 #define SUBTARGET_SWITCHES
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index a7769e3..2426db5 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -8744,21 +8744,6 @@
   [(set_attr "type" "multi")
    (set_attr "length" "3")])
 
-(define_insn "return"
-  [(return)
-   (use (reg:SI 31))]
-  "! TARGET_EPILOGUE"
-  "* return output_return (operands);"
-  [(set_attr "type" "return")])
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SI 1 "arith_operand" "rI"))
-   (parallel [(return)
-	      (use (reg:SI 31))])]
-  "sparc_return_peephole_ok (operands[0], operands[1])"
-  "return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0")
-
 (define_insn "nop"
   [(const_int 0)]
   ""
@@ -9155,14 +9140,14 @@
 		   (compare:CC (match_dup 1) (const_int 0)))])]
   "")
 
-;; Return peepholes.  First the "normal" ones.
-;; These are necessary to catch insns ending up in the epilogue delay list.
+;; Return peepholes.  These are generated by sparc_nonflat_function_epilogue
+;; who then immediately calls final_scan_insn.
 
 (define_insn "*return_qi"
   [(set (match_operand:QI 0 "restore_operand" "")
 	(match_operand:QI 1 "arith_operand" "rI"))
    (return)]
-  "! TARGET_EPILOGUE"
+  "sparc_emitting_epilogue"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -9180,7 +9165,7 @@
   [(set (match_operand:HI 0 "restore_operand" "")
 	(match_operand:HI 1 "arith_operand" "rI"))
    (return)]
-  "! TARGET_EPILOGUE"
+  "sparc_emitting_epilogue"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -9198,7 +9183,7 @@
   [(set (match_operand:SI 0 "restore_operand" "")
 	(match_operand:SI 1 "arith_operand" "rI"))
    (return)]
-  "! TARGET_EPILOGUE"
+  "sparc_emitting_epilogue"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -9212,15 +9197,11 @@
   [(set_attr "type" "multi")
    (set_attr "length" "2")])
 
-;; The following pattern is only generated by delayed-branch scheduling,
-;; when the insn winds up in the epilogue.  This can happen not only when
-;; ! TARGET_FPU because we move complex types around by parts using
-;; SF mode SUBREGs.
 (define_insn "*return_sf_no_fpu"
   [(set (match_operand:SF 0 "restore_operand" "=r")
 	(match_operand:SF 1 "register_operand" "r"))
    (return)]
-  "! TARGET_EPILOGUE"
+  "sparc_emitting_epilogue"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -9237,7 +9218,7 @@
   [(set (match_operand:DF 0 "restore_operand" "=r")
 	(match_operand:DF 1 "register_operand" "r"))
    (return)]
-  "! TARGET_EPILOGUE && TARGET_ARCH64"
+  "sparc_emitting_epilogue && TARGET_ARCH64"
   "*
 {
   if (IN_OR_GLOBAL_P (operands[1]))
@@ -9253,7 +9234,7 @@
 	(plus:SI (match_operand:SI 1 "register_operand" "r")
 		 (match_operand:SI 2 "arith_operand" "rI")))
    (return)]
-  "! TARGET_EPILOGUE"
+  "sparc_emitting_epilogue"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -9274,7 +9255,7 @@
 	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
 		   (match_operand:SI 2 "immediate_operand" "in")))
    (return)]
-  "! TARGET_EPILOGUE && ! TARGET_CM_MEDMID"
+  "sparc_emitting_epilogue && ! TARGET_CM_MEDMID"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -9292,7 +9273,7 @@
   [(set (match_operand:DI 0 "restore_operand" "")
 	(match_operand:DI 1 "arith_double_operand" "rHI"))
    (return)]
-  "TARGET_ARCH64 && ! TARGET_EPILOGUE"
+  "sparc_emitting_epilogue && TARGET_ARCH64"
   "ret\;restore %%g0, %1, %Y0"
   [(set_attr "type" "multi")
    (set_attr "length" "2")])
@@ -9302,7 +9283,7 @@
 	(plus:DI (match_operand:DI 1 "arith_operand" "%r")
 		 (match_operand:DI 2 "arith_double_operand" "rHI")))
    (return)]
-  "TARGET_ARCH64 && ! TARGET_EPILOGUE"
+  "sparc_emitting_epilogue && TARGET_ARCH64"
   "ret\;restore %r1, %2, %Y0"
   [(set_attr "type" "multi")
    (set_attr "length" "2")])
@@ -9312,18 +9293,16 @@
 	(lo_sum:DI (match_operand:DI 1 "arith_operand" "%r")
 		   (match_operand:DI 2 "immediate_operand" "in")))
    (return)]
-  "TARGET_ARCH64 && ! TARGET_EPILOGUE && ! TARGET_CM_MEDMID"
+  "sparc_emitting_epilogue && TARGET_ARCH64 && ! TARGET_CM_MEDMID"
   "ret\;restore %r1, %%lo(%a2), %Y0"
   [(set_attr "type" "multi")
    (set_attr "length" "2")])
 
-;; The following pattern is only generated by delayed-branch scheduling,
-;; when the insn winds up in the epilogue.
 (define_insn "*return_sf"
   [(set (reg:SF 32)
 	(match_operand:SF 0 "register_operand" "f"))
    (return)]
-  "! TARGET_EPILOGUE"
+  "sparc_emitting_epilogue"
   "ret\;fmovs\\t%0, %%f0"
   [(set_attr "type" "multi")
    (set_attr "length" "2")])
diff --git a/gcc/config/sparc/splet.h b/gcc/config/sparc/splet.h
index d2ef4fb..0d3f054 100644
--- a/gcc/config/sparc/splet.h
+++ b/gcc/config/sparc/splet.h
@@ -20,7 +20,7 @@ the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
 #undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
+#define TARGET_DEFAULT MASK_APP_REGS
 
 #define CPP_PREDEFINES "-Dsparc -Acpu=sparc -Amachine=sparc" 
 
diff --git a/gcc/config/sparc/vxsparc64.h b/gcc/config/sparc/vxsparc64.h
index ecfe25b..358f2c0 100644
--- a/gcc/config/sparc/vxsparc64.h
+++ b/gcc/config/sparc/vxsparc64.h
@@ -71,7 +71,7 @@ Boston, MA 02111-1307, USA.  */
 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) -DCPU=ULTRASPARC -D__CPU__=CPU"
 
 #undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_APP_REGS | MASK_EPILOGUE | MASK_FPU \
+#define TARGET_DEFAULT (MASK_APP_REGS | MASK_FPU \
 			| MASK_LONG_DOUBLE_128 | MASK_64BIT)
 
 #undef SPARC_DEFAULT_CMODEL
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c26d183..eb800ee 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -349,10 +349,10 @@ in the following sections.
 -mcmodel=@var{code-model} @gol
 -m32  -m64 @gol
 -mapp-regs  -mbroken-saverestore  -mcypress @gol
--mepilogue  -mfaster-structs  -mflat @gol
+-mfaster-structs  -mflat @gol
 -mfpu  -mhard-float  -mhard-quad-float @gol
 -mimpure-text  -mlive-g0  -mno-app-regs @gol
--mno-epilogue  -mno-faster-structs  -mno-flat  -mno-fpu @gol
+-mno-faster-structs  -mno-flat  -mno-fpu @gol
 -mno-impure-text  -mno-stack-bias  -mno-unaligned-doubles @gol
 -msoft-float  -msoft-quad-float  -msparclite  -mstack-bias @gol
 -msupersparc  -munaligned-doubles  -mv8}
@@ -5164,18 +5164,6 @@ emulates the effect of the instruction.  Because of the trap handler overhead,
 this is much slower than calling the ABI library routines.  Thus the
 @option{-msoft-quad-float} option is the default.
 
-@item -mno-epilogue
-@itemx -mepilogue
-@opindex mno-epilogue
-@opindex mepilogue
-With @option{-mepilogue} (the default), the compiler always emits code for
-function exit at the end of each function.  Any function exit in
-the middle of the function (such as a return statement in C) will
-generate a jump to the exit code at the end of the function.
-
-With @option{-mno-epilogue}, the compiler tries to emit exit code inline
-at every function exit.
-
 @item -mno-flat
 @itemx -mflat
 @opindex mno-flat