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| author | Richard Earnshaw <rearnsha@arm.com> | 2006-02-09 15:18:10 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2006-02-09 15:18:10 +0000 |
| commit | f9fa4363858bbe008735b45d15b0c031ce5ca08b (patch) | |
| tree | aafe3e634591fa8f078feac389dff9c5febacdaf /gcc | |
| parent | 5230d884913ae19b5310f200b96fcaa1cf64a7db (diff) | |
| download | gcc-f9fa4363858bbe008735b45d15b0c031ce5ca08b.zip gcc-f9fa4363858bbe008735b45d15b0c031ce5ca08b.tar.gz gcc-f9fa4363858bbe008735b45d15b0c031ce5ca08b.tar.bz2 | |
arm.md (tlobits_cbranch): New pattern.
* arm.md (tlobits_cbranch): New pattern.
* arm.h (arm_select_cc_mode): For thumb, only return CC_Nmode if
testing a single bit.
From-SVN: r110803
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 3 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 44 |
3 files changed, 52 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c339897..f3835d8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2006-02-09 Richard Earnshaw <richard.earnshaw@arm.com> + + * arm.md (tlobits_cbranch): New pattern. + * arm.h (arm_select_cc_mode): For thumb, only return CC_Nmode if + testing a single bit. + 2006-02-09 Andrew Pinski <pinskia@physics.uc.edu> PR tree-opt/26179 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index c7cb82c..4e9ae1b 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -6748,7 +6748,8 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) if (TARGET_THUMB && GET_MODE (x) == SImode && (op == EQ || op == NE) - && (GET_CODE (x) == ZERO_EXTRACT)) + && GET_CODE (x) == ZERO_EXTRACT + && XEXP (x, 1) == const1_rtx) return CC_Nmode; /* An operation that sets the condition codes as a side-effect, the diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 3853afc..53b633d 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -6028,6 +6028,50 @@ (const_int 8))))] ) +(define_insn "*tlobits_cbranch" + [(set (pc) + (if_then_else + (match_operator 0 "equality_operator" + [(zero_extract:SI (match_operand:SI 1 "s_register_operand" "l") + (match_operand:SI 2 "const_int_operand" "i") + (const_int 0)) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (match_scratch:SI 4 "=l"))] + "TARGET_THUMB" + "* + { + rtx op[3]; + op[0] = operands[4]; + op[1] = operands[1]; + op[2] = GEN_INT (32 - INTVAL (operands[2])); + + output_asm_insn (\"lsl\\t%0, %1, %2\", op); + switch (get_attr_length (insn)) + { + case 4: return \"b%d0\\t%l3\"; + case 6: return \"b%D0\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; + default: return \"b%D0\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; + } + }" + [(set (attr "far_jump") + (if_then_else + (eq_attr "length" "8") + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -250)) + (le (minus (match_dup 3) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) + (le (minus (match_dup 3) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))))] +) + (define_insn "*tstsi3_cbranch" [(set (pc) (if_then_else |