gcc/

	From Michael Frysinger  <michael.frysinger@analog.com>
	* config/bfin/bfin.c (bfin_cpus[]): Add 0.1 for bf522, bf523, bf524,
	bf525, bf526, bf527, bf542, bf544, bf547, bf548, and bf549.  Add 0.2
	for bf538.

gcc/testsuite/
	From Mike Frysinger  <michael.frysinger@analog.com>
	* gcc.target/bfin/mcpu-bf522.c: Check SILICON_REVISION is 0x0001.
	* gcc.target/bfin/mcpu-bf523.c: Likewise.
	* gcc.target/bfin/mcpu-bf524.c: Likewise.
	* gcc.target/bfin/mcpu-bf525.c: Likewise.
	* gcc.target/bfin/mcpu-bf526.c: Likewise.
	* gcc.target/bfin/mcpu-bf527.c: Likewise.
	* gcc.target/bfin/mcpu-bf542.c: Likewise.
	* gcc.target/bfin/mcpu-bf544.c: Likewise.
	* gcc.target/bfin/mcpu-bf547.c: Likewise.
	* gcc.target/bfin/mcpu-bf548.c: Likewise.
	* gcc.target/bfin/mcpu-bf549.c: Likewise.

From-SVN: r139935

14 files changed, 68 insertions, 22 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5f6fe22..894a32d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2008-09-03  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	From Michael Frysinger  <michael.frysinger@analog.com>
+	* config/bfin/bfin.c (bfin_cpus[]): Add 0.1 for bf522, bf523, bf524,
+	bf525, bf526, bf527, bf542, bf544, bf547, bf548, and bf549.  Add 0.2
+	for bf538.
+
 2008-09-03  Hari Sandanagobalane  <hariharan@picochip.com>
 
 	Add picoChip port.
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index bbd8223..86195ed 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -114,21 +114,33 @@ struct bfin_cpu
 
 struct bfin_cpu bfin_cpus[] =
 {
+  {"bf522", BFIN_CPU_BF522, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf522", BFIN_CPU_BF522, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf523", BFIN_CPU_BF523, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf523", BFIN_CPU_BF523, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf524", BFIN_CPU_BF524, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf524", BFIN_CPU_BF524, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf525", BFIN_CPU_BF525, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf525", BFIN_CPU_BF525, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf526", BFIN_CPU_BF526, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf526", BFIN_CPU_BF526, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf527", BFIN_CPU_BF527, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf527", BFIN_CPU_BF527, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
@@ -178,6 +190,8 @@ struct bfin_cpu bfin_cpus[] =
    WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf538", BFIN_CPU_BF538, 0x0003,
    WA_SPECULATIVE_LOADS | WA_RETS},
+  {"bf538", BFIN_CPU_BF538, 0x0002,
+   WA_SPECULATIVE_LOADS | WA_RETS},
 
   {"bf539", BFIN_CPU_BF539, 0x0004,
    WA_SPECULATIVE_LOADS | WA_RETS},
@@ -186,18 +200,28 @@ struct bfin_cpu bfin_cpus[] =
   {"bf539", BFIN_CPU_BF539, 0x0002,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf542", BFIN_CPU_BF542, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf542", BFIN_CPU_BF542, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf544", BFIN_CPU_BF544, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf544", BFIN_CPU_BF544, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf547", BFIN_CPU_BF547, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf547", BFIN_CPU_BF547, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf548", BFIN_CPU_BF548, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf548", BFIN_CPU_BF548, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf549", BFIN_CPU_BF549, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf549", BFIN_CPU_BF549, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f76865e..3cb12d1 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,18 @@
+2008-09-03  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	From Mike Frysinger  <michael.frysinger@analog.com>
+	* gcc.target/bfin/mcpu-bf522.c: Check SILICON_REVISION is 0x0001.
+	* gcc.target/bfin/mcpu-bf523.c: Likewise.
+	* gcc.target/bfin/mcpu-bf524.c: Likewise.
+	* gcc.target/bfin/mcpu-bf525.c: Likewise.
+	* gcc.target/bfin/mcpu-bf526.c: Likewise.
+	* gcc.target/bfin/mcpu-bf527.c: Likewise.
+	* gcc.target/bfin/mcpu-bf542.c: Likewise.
+	* gcc.target/bfin/mcpu-bf544.c: Likewise.
+	* gcc.target/bfin/mcpu-bf547.c: Likewise.
+	* gcc.target/bfin/mcpu-bf548.c: Likewise.
+	* gcc.target/bfin/mcpu-bf549.c: Likewise.
+
 2008-09-02  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 
 	* gcc.c-torture/compile/pr33009.c: xfail on hppa*-*-*.
diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf522.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf522.c
index 205e37f..7a1b3f4 100644
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf522.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf522.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf523.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf523.c
index eb21e67..46bc9c1 100644
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf523.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf523.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf524.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf524.c
index 7be6355..714be44 100644
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf524.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf524.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf525.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf525.c
index 21dc2be..0c1c60c 100644
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf525.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf525.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf526.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf526.c
index bd1197e..43d09e1 100644
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf526.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf526.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf527.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf527.c
index d419dd7..179d587 100644
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf527.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf527.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c
index f36b163..1999367 100644
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c
index d1a0045..e23abe0 100644
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c
index cdf1995..fa34108 100644
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c
index 2689eb2..bc1bcd8 100644
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c
index 01e068a..d60ee3f 100644
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED