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| author | Levy Hsu <admin@levyhsu.com> | 2024-09-04 16:34:04 +0930 |
|---|---|---|
| committer | Levy Hsu <admin@levyhsu.com> | 2024-09-12 06:33:33 +0000 |
| commit | 89d50c45048e5d7230ddde9afc8fbc83143e34cb (patch) | |
| tree | 151c364b91b09c4eed02657caafccfb258e0b4ea /gcc | |
| parent | 3f212eabbba3edc1827d6da53cf6d5a64c6524f0 (diff) | |
| download | gcc-89d50c45048e5d7230ddde9afc8fbc83143e34cb.zip gcc-89d50c45048e5d7230ddde9afc8fbc83143e34cb.tar.gz gcc-89d50c45048e5d7230ddde9afc8fbc83143e34cb.tar.bz2 | |
i386: Enable V2BF/V4BF vec_cmp with AVX10.2 vcmppbf16
gcc/ChangeLog:
* config/i386/i386.cc (ix86_get_mask_mode):
Enable BFmode for targetm.vectorize.get_mask_mode with AVX10.2.
* config/i386/mmx.md (vec_cmp<mode>qi):
Implement vec_cmpv2bfqi and vec_cmpv4bfqi.
gcc/testsuite/ChangeLog:
* gcc.target/i386/part-vect-vec_cmpbf.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/i386.cc | 3 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 17 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/part-vect-vec_cmpbf.c | 26 |
3 files changed, 45 insertions, 1 deletions
diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 4532012..7dbae1d 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -24682,7 +24682,8 @@ ix86_get_mask_mode (machine_mode data_mode) /* AVX512FP16 only supports vector comparison to kmask for _Float16. */ || (TARGET_AVX512VL && TARGET_AVX512FP16 - && GET_MODE_INNER (data_mode) == E_HFmode)) + && GET_MODE_INNER (data_mode) == E_HFmode) + || (TARGET_AVX10_2_256 && GET_MODE_INNER (data_mode) == E_BFmode)) { if (elem_size == 4 || elem_size == 8 diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 4bc191b..2f8d958 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -2290,6 +2290,23 @@ DONE; }) +;;This instruction does not generate floating point exceptions +(define_expand "vec_cmp<mode>qi" + [(set (match_operand:QI 0 "register_operand") + (match_operator:QI 1 "" + [(match_operand:VBF_32_64 2 "register_operand") + (match_operand:VBF_32_64 3 "nonimmediate_operand")]))] + "TARGET_AVX10_2_256" +{ + rtx op2 = lowpart_subreg (V8BFmode, + force_reg (<MODE>mode, operands[2]), <MODE>mode); + rtx op3 = lowpart_subreg (V8BFmode, + force_reg (<MODE>mode, operands[3]), <MODE>mode); + + emit_insn (gen_vec_cmpv8bfqi (operands[0], operands[1], op2, op3)); + DONE; +}) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel half-precision floating point rounding operations. diff --git a/gcc/testsuite/gcc.target/i386/part-vect-vec_cmpbf.c b/gcc/testsuite/gcc.target/i386/part-vect-vec_cmpbf.c new file mode 100644 index 0000000..0bb720b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/part-vect-vec_cmpbf.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx10.2" } */ +/* { dg-final { scan-assembler-times "vcmppbf16" 10 } } */ + +typedef __bf16 __attribute__((__vector_size__ (4))) v2bf; +typedef __bf16 __attribute__((__vector_size__ (8))) v4bf; + + +#define VCMPMN(type, op, name) \ +type \ +__attribute__ ((noinline, noclone)) \ +vec_cmp_##type##type##name (type a, type b) \ +{ \ + return a op b; \ +} + +VCMPMN (v4bf, <, lt) +VCMPMN (v2bf, <, lt) +VCMPMN (v4bf, <=, le) +VCMPMN (v2bf, <=, le) +VCMPMN (v4bf, >, gt) +VCMPMN (v2bf, >, gt) +VCMPMN (v4bf, >=, ge) +VCMPMN (v2bf, >=, ge) +VCMPMN (v4bf, ==, eq) +VCMPMN (v2bf, ==, eq) |