Daily bump.

10 files changed, 589 insertions, 1 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 91a24a9..bf4ad62 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,274 @@
+2024-09-03  YunQiang Su  <syq@gcc.gnu.org>
+
+	* config/mips/mips-msa.md: (MSA_NO_HADD): we have HADD for
+	S8/U8/S16/U16/S32/U32 only.
+	(reduc_smin_scal_<mode>): New define pattern.
+	(reduc_smax_scal_<mode>): Ditto.
+	(reduc_umin_scal_<mode>): Ditto.
+	(reduc_umax_scal_<mode>): Ditto.
+	(reduc_plus_scal_<mode>): Ditto.
+	(reduc_plus_scal_v4si): Ditto.
+	(reduc_plus_scal_v8hi): Ditto.
+	(reduc_plus_scal_v16qi): Ditto.
+	(reduc_<optab>_scal_<mode>): Ditto.
+	* config/mips/mips-protos.h: New function mips_expand_msa_reduc.
+	* config/mips/mips.cc: New function mips_expand_msa_reduc.
+	* config/mips/mips.md: Define any_bitwise iterator.
+
+2024-09-02  Alexandre Oliva  <oliva@adacore.com>
+
+	PR d/115295
+	* doc/sourcebuild.texi (dg-additional-sources): Add linkonly.
+
+2024-09-02  Andrew Stubbs  <ams@baylibre.com>
+
+	* config/gcn/gcn-opts.h (TARGET_GCN5_PLUS): Delete.
+	(TARGET_GLOBAL_ADDRSPACE): Delete.
+	(TARGET_FLAT_OFFSETS): Delete.
+	(TARGET_EXPLICIT_CARRY): Delete.
+	(TARGET_MULTIPLY_IMMEDIATE): Delete.
+	* config/gcn/gcn-valu.md (*mov<mode>): Rename "gcn_version" to "cdna".
+	(*mov<mode>_4reg): Likewise.
+	(@mov<mode>_sgprbase): Likwise.
+	(gather<mode>_insn_1offset<exec>): Likewise.
+	(gather<mode>_insn_1offset_ds<exec>): Likewise.
+	(gather<mode>_insn_2offsets<exec>): Likewise.
+	(scatter<mode>_insn_1offset<exec_scatter>): Likewise.
+	(scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
+	(scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
+	(gather<mode>_insn_1offset<exec>): Remove TARGET_FLAT_OFFSETS
+	conditionals.
+	(scatter<mode>_insn_1offset<exec_scatter>): Likewise.
+	(scatter<mode>_insn_1offset<exec_scatter>): Likewise.
+	(add<mode>3<exec_clobber>): Use "_co" instead of "%^".
+	(add<mode>3_dup<exec_clobber>): Likewise.
+	(add<mode>3_vcc<exec_vcc>): Likewise.
+	(add<mode>3_vcc_dup<exec_vcc>): Likewise.
+	(addc<mode>3<exec_vcc>): Likewise.
+	(sub<mode>3<exec_clobber>): Likewise.
+	(sub<mode>3_vcc<exec_vcc>): Likewise.
+	(subc<mode>3<exec_vcc>): Likewise.
+	(*plus_carry_dpp_shr_<mode>): Likewise.
+	(*plus_carry_in_dpp_shr_<mode>): Likewise.
+	* config/gcn/gcn.cc (gcn_flat_address_p): Remove TARGET_FLAT_OFFSETS
+	conditionals.
+	(gcn_addr_space_legitimate_address_p): Likewise.
+	(gcn_addr_space_legitimize_address): Likewise.
+	(gcn_expand_scalar_to_vector_address): Likewise.
+	(print_operand_address): Likewise, and TARGET_GLOBAL_ADDRSPACE also.
+	(print_operand): Remove "%^" operand code.
+	Remove TARGET_GLOBAL_ADDRSPACE assertion.
+	* config/gcn/gcn.h (STACK_ADDR_SPACE): Remove GCN5 conditional.
+	* config/gcn/gcn.md (gcn_version): Rename attribute ...
+	(cdna): ... to this, and remove the gcn3 and gcn5 values.
+	(enabled): Replace old "gcn_version" logic with new "cdna" logic.
+	(*mov<mode>_insn): Rename "gcn_version" to "cdna".
+	(*movti_insn): Likewise.
+	(addsi3): Use "_co" instead of "%^".
+	(addsi3_scalar_carry): Likewise.
+	(addsi3_scalar_carry_cst): Likewise.
+	(addcsi3_scalar): Likewise.
+	(addcsi3_scalar_zero): Likewise.
+	(addptrdi3): Likewise.
+	(subsi3): Likewise.
+	(<su>mulsi3_highpart): Remove TARGET_MULTIPLY_IMMEDIATE conditions.
+	(<su>mulsi3_highpart_reg): Remove "gcn_version" attribute.
+	(muldi3): Likewise.
+	(atomic_fetch_<bare_mnemonic><mode>): Likewise.
+	(atomic_<bare_mnemonic><mode>): Likewise.
+	(sync_compare_and_swap<mode>_insn): Likewise.
+	(atomic_load<mode>): Likewise.
+	(atomic_store<mode>): Likewise.
+	(atomic_exchange<mode>): Likewise.
+	(<su>mulsi3_highpart_imm): Remove both TARGET_MULTIPLY_IMMEDIATE and
+	"gcn_version".
+	(<su>mulsidi3): Likewise.
+	(<su>mulsidi3_imm): Likewise.
+
+2024-09-02  Andrew Stubbs  <ams@baylibre.com>
+
+	* config/gcn/gcn-opts.h (enum gcn_isa): Delete ISA_GCN3.
+	(TARGET_GCN3): Delete.
+	(TARGET_GCN3_PLUS): Delete.
+	(TARGET_M0_LDS_LIMIT): Delete.
+	* config/gcn/gcn-valu.md
+	(gather<mode>_insn_1offset<exec>): Remove TARGET_GCN3 from conditions.
+	(*<reduc_op>_dpp_shr_<mode>): Likewise.
+	* config/gcn/gcn.cc (enum gcn_isa): Change default to ISA_GCN5.
+	(gcn_expand_prologue): Remove TARGET_M0_LDS_LIMIT feature.
+	(gcn_expand_reduc_scalar): Remove TARGET_GCN3 conditions.
+	* config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Remove TARGET_GCN3.
+
+2024-09-02  Andrew Stubbs  <ams@baylibre.com>
+
+	* config.gcc (amdgcn-*-*): Remove "fiji" from with_arch checks.
+	* config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): Remove fiji alternative.
+	(NO_XNACK): Likewise.
+	(NO_SRAM_ECC): Likewise.
+	(ASM_SPEC): Remove "%{}" around ABI_VERSION_SPEC.
+	* config/gcn/gcn-opts.h (enum processor_type): Remove PROCESSOR_FIJI.
+	(TARGET_FIJI): Delete.
+	* config/gcn/gcn.cc (gcn_option_override): Remove Fiji.
+	(gcn_omp_device_kind_arch_isa): Likewise.
+	(output_file_start): Likewise.
+	* config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Likewise.
+	* config/gcn/gcn.opt (gpu_type): Likewise.
+	(march, mtune): Change default to PROCESSOR_VEGA10.
+	* config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX803): Delete.
+	(copy_early_debug_info): Remove elf_flags_actual.
+	Use ELFABIVERSION_AMDGPU_HSA_V4 unconditionally.
+	(get_arch): Remove Fiji.
+	(main): Remove gfx803.
+	* config/gcn/t-omp-device
+	(omp-device-properties-gcn): Remove fiji and gfx803.
+	* doc/install.texi (amdgcn*-*-*): Remove fiji and special instructions.
+	* doc/invoke.texi: Remove fiji.
+
+2024-09-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* doc/gimple.texi (gimple_asm_basic_p): Document.
+	(gimple_asm_set_basic): Likewise.
+	* gimple.h (GF_ASM_INPUT): Rename to...
+	(GF_ASM_BASIC): ...this.
+	(gimple_asm_set_input): Rename to...
+	(gimple_asm_set_basic): ...this.
+	(gimple_asm_input_p): Rename to...
+	(gimple_asm_basic_p): ...this.
+	* cfgexpand.cc (expand_asm_stmt): Update after above renaming.
+	* gimple.cc (gimple_asm_clobbers_memory_p): Likewise.
+	* gimplify.cc (gimplify_asm_expr): Likewise.
+	* ipa-icf-gimple.cc (func_checker::compare_gimple_asm): Likewise.
+	* tree-cfg.cc (stmt_can_terminate_bb_p): Likewise.
+
+2024-09-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* doc/generic.texi (ASM_BASIC_P): Document.
+	* tree.h (ASM_INPUT_P): Rename to...
+	(ASM_BASIC_P): ...this.
+	(ASM_VOLATILE_P, ASM_INLINE_P): Reindent.
+	* gimplify.cc (gimplify_asm_expr): Update after above renaming.
+	* tree-core.h (tree_base): Likewise.
+
+2024-09-02  Tobias Burnus  <tburnus@baylibre.com>
+
+	* lto-wrapper.cc (run_gcc): Honor -save-temps for
+	makefile name.
+
+2024-09-02  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/116486
+	* gimple-range-op.cc (cfn_clz::fold_range): If lh is [0,0]
+	and mini is -1, return [-1,-1] range rather than [prec-1,prec-1].
+
+2024-09-02  Richard Biener  <rguenther@suse.de>
+
+	* tree-vectorizer.h (_slp_tree::ldst_lanes): New flag to mark
+	load, store and permute nodes.
+	* tree-vect-slp.cc (_slp_tree::_slp_tree): Initialize ldst_lanes.
+	(vect_build_slp_instance): For stores iff the target prefers
+	store-lanes discover single-lane sub-groups, do not perform
+	interleaving lowering but mark the node with ldst_lanes.
+	Also allow i == 0 - fatal failure - for splitting up a store group
+	when we're not doing single-lane discovery already.
+	(vect_lower_load_permutations): When the target supports
+	load lanes and the loads all fit the pattern split out
+	a single level of permutes only and mark the load and
+	permute nodes with ldst_lanes.
+	(vectorizable_slp_permutation_1): Handle the load-lane permute
+	forwarding of vector defs.
+	(vect_analyze_slp): After SLP pattern recog is finished see if
+	there are any SLP instances that would benefit from using
+	load/store-lanes and re-discover those with forced single lanes.
+	* tree-vect-stmts.cc (get_group_load_store_type): Support
+	load/store-lanes for SLP.
+	(vectorizable_store): Support SLP code generation for store-lanes.
+	(vectorizable_load): Support SLP code generation for load-lanes.
+	* tree-vect-loop.cc (vect_analyze_loop_2): Do not cancel SLP
+	when store-lanes can be used.
+
+2024-09-02  Richard Biener  <rguenther@suse.de>
+
+	* tree-vect-slp.cc (vect_build_slp_tree_1): Handle NULL stmt.
+	(vect_build_slp_tree_2): Likewise.  Release load permutation
+	when there's a NULL in SLP_TREE_SCALAR_STMTS and assert there's
+	no actual permutation in that case.
+	(vllp_cmp): New function.
+	(vect_lower_load_permutations): Likewise.
+	(vect_analyze_slp): Call it.
+
+2024-09-02  Xianmiao Qu  <cooper.qu@linux.alibaba.com>
+
+	* config/riscv/riscv.cc (riscv_rtx_costs): Optimize the cost of the
+	DFmode register move for RV32.
+
+2024-09-02  Jeff Law  <jlaw@ventanamicro.com>
+
+	PR rtl-optimization/116544
+	* ext-dce.cc (ext_dce_process_uses): Fix thinko in promoted subreg
+	handling.
+
+2024-09-02  Levy Hsu  <admin@levyhsu.com>
+
+	* config/i386/i386-expand.cc (ix86_use_mask_cmp_p): Add BFmode
+	for int mask cmp.
+	* config/i386/sse.md (vec_cmp<mode><avx512fmaskmodelower>): New
+	vec_cmp expand for VBF modes.
+
+2024-09-02  Levy Hsu  <admin@levyhsu.com>
+
+	* config/i386/sse.md: Expand VF2H to VF2HB with VBF modes.
+
+2024-09-02  Levy Hsu  <admin@levyhsu.com>
+
+	* config/i386/sse.md
+	(<code><mode>3): New define expand pattern for BF smaxmin.
+
+2024-09-02  Levy Hsu  <admin@levyhsu.com>
+
+	* config/i386/sse.md: Add V8BF/V16BF/V32BF to mode iterator FMAMODEM.
+
+2024-09-02  Levy Hsu  <admin@levyhsu.com>
+
+	* config/i386/sse.md (div<mode>3): New expander for BFmode div.
+	(VF_BHSD): New mode iterator with vector BFmodes.
+	(<insn><mode>3<mask_name><round_name>): Change mode to VF_BHSD.
+	(mul<mode>3<mask_name><round_name>): Likewise.
+
+2024-09-02  Hu, Lin1  <lin1.hu@intel.com>
+
+	* config/i386/i386-expand.cc (ix86_expand_fp_compare): Add UNSPEC to
+	support the optimization.
+	* config/i386/i386.cc (ix86_fp_compare_code_to_integer): Add NE/EQ.
+	* config/i386/i386.md (*cmpx<unord><MODEF:mode>): New define_insn.
+	(*cmpx<unord>hf): Ditto.
+	* config/i386/predicates.md (ix86_trivial_fp_comparison_operator):
+	Add ne/eq.
+
+2024-09-02  Hu, Lin1  <lin1.hu@intel.com>
+
+	* match.pd: Optimize (and ordered non-equal) to
+	(not (or unordered  equal))
+
+2024-09-02  Haochen Jiang  <haochen.jiang@intel.com>
+
+	* config/i386/sse.md (VI1_AVX512VNNIBW): New.
+	(VI2_AVX10_2): Ditto.
+	(sdot_prod<mode>): Add AVX10.2
+	to auto vectorize and combine 512 bit part.
+	(udot_prod<mode>): Ditto.
+	(sdot_prodv64qi): Removed.
+	(udot_prodv64qi): Ditto.
+	(usdot_prod<mode>): Add AVX10.2 to auto vectorize.
+	(udot_prod<mode>): Ditto.
+
+2024-09-02  Pan Li  <pan2.li@intel.com>
+
+	* config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Merge
+	the zero_extend handing from func riscv_gen_unsigned_xmode_reg.
+	(riscv_gen_unsigned_xmode_reg): Remove.
+	(riscv_expand_ussub): Leverage riscv_gen_zero_extend_rtx
+	instead of riscv_gen_unsigned_xmode_reg.
+
 2024-09-01  Andrew Pinski  <quic_apinski@quicinc.com>
 
 	PR tree-optimization/116554
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 18af8d7..a1e4e7f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20240902
+20240903
diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index a6e9d36..08f1f4e 100644
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,61 @@
+2024-09-02  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* gcc-interface/decl.cc (gnat_to_gnu_entity): Cap the Esize of a
+	floating-point type to the size of the widest format supported in
+	hardware if it is explicity defined.
+
+2024-09-02  Viljar Indus  <indus@adacore.com>
+
+	* doc/gnat_ugn/building_executable_programs_with_gnat.rst: update
+	documentation for the -gnatw_l switch.
+	* usage.adb: Add -gnatw_l entry.
+	* gnat_ugn.texi: Regenerate.
+
+2024-09-02  Ronan Desplanques  <desplanques@adacore.com>
+
+	* gnatcmd.adb (GNATCmd): Fix standard output stream.
+
+2024-09-02  Ronan Desplanques  <desplanques@adacore.com>
+
+	* doc/gnat_ugn/building_executable_programs_with_gnat.rst: Fix
+	minor issues.
+	* gnat_ugn.texi: Regenerate.
+
+2024-09-02  Bob Duff  <duff@adacore.com>
+
+	* doc/gnat_rm/gnat_language_extensions.rst: I assume "extended set
+	of extensions" was a typo for "experimental set of extensions",
+	because "extended extensions" is repetitive and redundant. "in
+	addition" clarifies that the one subsumes the other. Add a
+	reminder at the start of each subsection about what switch/pragma
+	enables what extensions. Add new section about "Inference of
+	Dependent Types in Generic Instantiations".
+	* gnat_rm.texi: Regenerate.
+
+2024-09-02  Patrick Bernardi  <bernardi@adacore.com>
+
+	* s-oscons-tmplt.c: Define sizes of pthread data types on FreeBSD.
+	* tracebak.c: Use GCC unwinder and adjust PC appropriately on
+	aarch64-freebsd.
+
+2024-09-02  Marc Poulhiès  <poulhies@adacore.com>
+
+	* exp_ch9.adb (Reset_Scopes_To): Adjust comment.
+	(Reset_Scopes_To.Reset_Scope): Adjust the scope reset for object
+	declaration. In particular, visit the children nodes if any. Also
+	extend the handling of other declarations to
+	N_Implicit_Label_Declaration.
+
+2024-09-02  Piotr Trojanek  <trojanek@adacore.com>
+
+	* exp_ch3.adb (Expand_N_Object_Declaration): Replace calls to Sloc
+	with uses of Loc; turn variable Prag into constant.
+
+2024-09-02  Piotr Trojanek  <trojanek@adacore.com>
+
+	* exp_imgv.adb (Expand_User_Defined_Enumeration_Image)
+	(Expand_Image_Attribute): Remove redundant guards.
+
 2024-08-29  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* sem_ch8.adb (Has_Private_With): Add test on Is_Entity_Name.
diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog
index 191cb02..53fcfcc 100644
--- a/gcc/c/ChangeLog
+++ b/gcc/c/ChangeLog
@@ -1,3 +1,7 @@
+2024-09-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* c-typeck.cc (build_asm_expr): Rename ASM_INPUT_P to ASM_BASIC_P.
+
 2024-08-31  Jakub Jelinek  <jakub@redhat.com>
 
 	PR c/116130
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 963a7ef..539fb6e 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,8 @@
+2024-09-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* pt.cc (tsubst_stmt): Rename ASM_INPUT_P to ASM_BASIC_P.
+	* parser.cc (cp_parser_asm_definition): Likewise.
+
 2024-08-31  Iain Sandoe  <iain@sandoe.co.uk>
 
 	* coroutines.cc (coro_build_frame_access_expr): New.
diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog
index e1bfdde..9c78661 100644
--- a/gcc/d/ChangeLog
+++ b/gcc/d/ChangeLog
@@ -1,3 +1,7 @@
+2024-09-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* toir.cc (IRVisitor): Rename ASM_INPUT_P to ASM_BASIC_P.
+
 2024-07-21  Sam James  <sam@gentoo.org>
 
 	* Make-lang.in (WARN_DFLAGS): Drop NOCOMMON_FLAG.
diff --git a/gcc/jit/ChangeLog b/gcc/jit/ChangeLog
index 32ba29a..0df9085 100644
--- a/gcc/jit/ChangeLog
+++ b/gcc/jit/ChangeLog
@@ -1,3 +1,8 @@
+2024-09-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* jit-playback.cc (playback::block::add_extended_asm):  Rename
+	ASM_INPUT_P to ASM_BASIC_P.
+
 2024-07-24  David Malcolm  <dmalcolm@redhat.com>
 
 	* jit-playback.cc (jit::playback_context::compile) Add a trailing
diff --git a/gcc/lto/ChangeLog b/gcc/lto/ChangeLog
index 718c556..9692d8b 100644
--- a/gcc/lto/ChangeLog
+++ b/gcc/lto/ChangeLog
@@ -1,3 +1,7 @@
+2024-09-02  Tobias Burnus  <tburnus@baylibre.com>
+
+	* lto.cc: Add missing HAVE_WORKING_FORK.
+
 2024-06-07  Simon Martin  <simon@nasilyan.com>
 
 	* lto-partition.cc: Define INCLUDE_VECTOR to avoid running into
diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index efa946d..61cbbca 100644
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,53 @@
+2024-09-02  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	PR modula2/116557
+	* gm2-lang.cc: Replace physical address with URL in GPL header.
+	* gm2-lang.h: Ditto.
+	* images/LICENSE.IMG: Ditto.
+	* m2-tree.def: Ditto.
+	* mc-boot/GIndexing.cc: Ditto.
+	* mc-boot/Gkeyc.cc: Ditto.
+	* mc-boot/Glists.cc: Ditto.
+	* mc-boot/GmcComp.cc: Ditto.
+	* mc-boot/GmcDebug.cc: Ditto.
+	* mc-boot/GmcFileName.cc: Ditto.
+	* mc-boot/GmcMetaError.cc: Ditto.
+	* mc-boot/GmcOptions.cc: Ditto.
+	* mc-boot/GmcPreprocess.cc: Ditto.
+	* mc-boot/GmcPretty.cc: Ditto.
+	* mc-boot/GmcPrintf.cc: Ditto.
+	* mc-boot/GmcQuiet.cc: Ditto.
+	* mc-boot/GmcReserved.cc: Ditto.
+	* mc-boot/GmcSearch.cc: Ditto.
+	* mc-boot/GmcStack.cc: Ditto.
+	* mc/Indexing.mod: Ditto.
+	* mc/keyc.mod: Ditto.
+	* mc/lists.mod: Ditto.
+	* mc/mcComp.mod: Ditto.
+	* mc/mcDebug.mod: Ditto.
+	* mc/mcFileName.mod: Ditto.
+	* mc/mcMetaError.mod: Ditto.
+	* mc/mcOptions.mod: Ditto.
+	* mc/mcPreprocess.mod: Ditto.
+	* mc/mcPretty.mod: Ditto.
+	* mc/mcPrintf.mod: Ditto.
+	* mc/mcQuiet.mod: Ditto.
+	* mc/mcReserved.mod: Ditto.
+	* mc/mcSearch.mod: Ditto.
+	* mc/mcStack.mod: Ditto.
+	* tools-src/buildpg: Ditto.
+	* tools-src/calcpath: Ditto.
+	* tools-src/checkmeta.py: Ditto.
+	* tools-src/def2doc.py: Ditto.
+	* tools-src/makeSystem: Ditto.
+	* tools-src/tidydates.py: Ditto.
+
+2024-09-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gm2-gcc/m2block.cc (flush_pending_note): Rename ASM_INPUT_P
+	to ASM_BASIC_P.
+	* gm2-gcc/m2statement.cc (m2statement_BuildAsm): Likewise.
+
 2024-08-30  Gaius Mulley  <gaiusmod2@gmail.com>
 
 	PR modula2/116181
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index cfe6a6e..d22338f 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,190 @@
+2024-09-03  YunQiang Su  <syq@gcc.gnu.org>
+
+	* gcc.target/mips/msa-reduc.c: New tests.
+
+2024-09-02  Jakub Jelinek  <jakub@redhat.com>
+
+	* gcc.target/i386/optimize_one.c: Add -msse2 to dg-options.
+
+2024-09-02  Alexandre Oliva  <oliva@adacore.com>
+
+	PR d/115295
+	* g++.dg/vect/pr95401.cc: Add linkonly to dg-additional-sources.
+	* g++.dg/vect/pr68762-1.cc: Likewise.
+	* g++.dg/vect/simd-clone-3.cc: Likewise.
+	* g++.dg/vect/simd-clone-5.cc: Likewise.
+	* gcc.dg/vect/vect-simd-clone-10.c: Likewise.  Drop dg-do run.
+	* gcc.dg/vect/vect-simd-clone-12.c: Likewise.  Likewise.
+	* lib/gcc-defs.exp (additional_sources_omit_on_compile): New.
+	(dg-additional-sources): Add to it on linkonly.
+	(dg-additional-files-options): Omit select sources on compile.
+
+2024-09-02  Alex Coplan  <alex.coplan@arm.com>
+
+	* gcc.dg-selftests/dg-final.exp: Load scanltrans.exp instead of
+	scanltranstree.exp.
+	* lib/gcc-dg.exp: Likewise.
+	* lib/scanltranstree.exp: Rename to ...
+	* lib/scanltrans.exp: ... this.
+
+2024-09-02  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/116486
+	* gcc.dg/bitint-109.c: New test.
+
+2024-09-02  Richard Biener  <rguenther@suse.de>
+
+	* gcc.dg/vect/slp-55.c: New testcase.
+	* gcc.dg/vect/slp-56.c: Likewise.
+	* gcc.dg/vect/slp-11c.c: Adjust.
+	* gcc.dg/vect/slp-53.c: Likewise.
+	* gcc.dg/vect/slp-cond-1.c: Likewise.
+	* gcc.dg/vect/vect-complex-5.c: Likewise.
+	* gcc.dg/vect/slp-1.c: Likewise.
+	* gcc.dg/vect/slp-54.c: Remove riscv XFAIL.
+	* gcc.dg/vect/slp-perm-5.c: Adjust.
+	* gcc.dg/vect/slp-perm-7.c: Likewise.
+	* gcc.dg/vect/slp-perm-8.c: Likewise.
+	* gcc.dg/vect/slp-multitypes-11.c: Likewise.
+	* gcc.dg/vect/slp-multitypes-11-big-array.c: Likewise.
+	* gcc.dg/vect/slp-perm-9.c: Remove expected SLP fail due to
+	three-vector permute.
+	* gcc.dg/vect/slp-perm-6.c: Remove XFAIL.
+	* gcc.dg/vect/slp-perm-1.c: Adjust.
+	* gcc.dg/vect/slp-perm-2.c: Likewise.
+	* gcc.dg/vect/slp-perm-3.c: Likewise.
+	* gcc.dg/vect/slp-perm-4.c: Likewise.
+	* gcc.dg/vect/pr68445.c: Likewise.
+	* gcc.dg/vect/slp-11b.c: Likewise.
+	* gcc.dg/vect/slp-2.c: Likewise.
+	* gcc.dg/vect/slp-23.c: Likewise.
+	* gcc.dg/vect/slp-33.c: Likewise.
+	* gcc.dg/vect/slp-42.c: Likewise.
+	* gcc.dg/vect/slp-46.c: Likewise.
+	* gcc.dg/vect/slp-perm-10.c: Likewise.
+
+2024-09-02  Richard Biener  <rguenther@suse.de>
+
+	* gcc.dg/vect/slp-11a.c: Expect SLP.
+	* gcc.dg/vect/slp-12a.c: Likewise.
+	* gcc.dg/vect/slp-51.c: New testcase.
+	* gcc.dg/vect/slp-52.c: New testcase.
+
+2024-09-02  Xianmiao Qu  <cooper.qu@linux.alibaba.com>
+
+	* gcc.target/riscv/rv32-movdf-cost.c: New test.
+
+2024-09-02  Jeff Law  <jlaw@ventanamicro.com>
+
+	PR rtl-optimization/116544
+	* gcc.dg/torture/pr116544.c: New test.
+
+2024-09-02  Levy Hsu  <admin@levyhsu.com>
+
+	* gcc.target/i386/avx10_2-512-bf-vector-cmpp-1.c: New test.
+	* gcc.target/i386/avx10_2-bf-vector-cmpp-1.c: Ditto.
+
+2024-09-02  Levy Hsu  <admin@levyhsu.com>
+
+	* gcc.target/i386/avx10_2-512-bf-vector-smaxmin-1.c: New test.
+	* gcc.target/i386/avx10_2-bf-vector-smaxmin-1.c: New test.
+
+2024-09-02  Levy Hsu  <admin@levyhsu.com>
+
+	* gcc.target/i386/avx10_2-512-bf-vector-fma-1.c: New test.
+	* gcc.target/i386/avx10_2-bf-vector-fma-1.c: New test.
+
+2024-09-02  Levy Hsu  <admin@levyhsu.com>
+
+	* gcc.target/i386/avx10_2-512-bf-vector-operations-1.c: New test.
+	* gcc.target/i386/avx10_2-bf-vector-operations-1.c: Ditto.
+
+2024-09-02  Hu, Lin1  <lin1.hu@intel.com>
+
+	* gcc.target/i386/avx10_2-compare-1b.c: New test.
+
+2024-09-02  Hu, Lin1  <lin1.hu@intel.com>
+
+	* gcc.target/i386/optimize_one.c: New test.
+
+2024-09-02  Haochen Jiang  <haochen.jiang@intel.com>
+
+	* gcc.target/i386/vnniint16-auto-vectorize-2.c: Only define
+	TEST when not defined.
+	* gcc.target/i386/vnniint8-auto-vectorize-2.c: Ditto.
+	* gcc.target/i386/vnniint16-auto-vectorize-3.c: New test.
+	* gcc.target/i386/vnniint16-auto-vectorize-4.c: Ditto.
+	* gcc.target/i386/vnniint8-auto-vectorize-3.c: Ditto.
+	* gcc.target/i386/vnniint8-auto-vectorize-4.c: Ditto.
+
+2024-09-02  Pan Li  <pan2.li@intel.com>
+
+	* gcc.target/riscv/sat_u_trunc-16.c: New test.
+	* gcc.target/riscv/sat_u_trunc-17.c: New test.
+	* gcc.target/riscv/sat_u_trunc-18.c: New test.
+	* gcc.target/riscv/sat_u_trunc-run-16.c: New test.
+	* gcc.target/riscv/sat_u_trunc-run-17.c: New test.
+	* gcc.target/riscv/sat_u_trunc-run-18.c: New test.
+
+2024-09-02  Pan Li  <pan2.li@intel.com>
+
+	* gcc.target/riscv/sat_u_trunc-10.c: New test.
+	* gcc.target/riscv/sat_u_trunc-11.c: New test.
+	* gcc.target/riscv/sat_u_trunc-12.c: New test.
+	* gcc.target/riscv/sat_u_trunc-run-10.c: New test.
+	* gcc.target/riscv/sat_u_trunc-run-11.c: New test.
+	* gcc.target/riscv/sat_u_trunc-run-12.c: New test.
+
+2024-09-02  Pan Li  <pan2.li@intel.com>
+
+	* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c: New test.
+
+2024-09-02  Pan Li  <pan2.li@intel.com>
+
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c: New test.
+
+2024-09-02  Pan Li  <pan2.li@intel.com>
+
+	* gcc.target/riscv/sat_u_sub-11.c: Adjust asm check.
+	* gcc.target/riscv/sat_u_sub-15.c: Ditto.
+	* gcc.target/riscv/sat_u_sub-19.c: Ditto.
+	* gcc.target/riscv/sat_u_sub-23.c: Ditto.
+	* gcc.target/riscv/sat_u_sub-27.c: Ditto.
+	* gcc.target/riscv/sat_u_sub-3.c: Ditto.
+	* gcc.target/riscv/sat_u_sub-31.c: Ditto.
+	* gcc.target/riscv/sat_u_sub-35.c: Ditto.
+	* gcc.target/riscv/sat_u_sub-39.c: Ditto.
+	* gcc.target/riscv/sat_u_sub-43.c: Ditto.
+	* gcc.target/riscv/sat_u_sub-47.c: Ditto.
+	* gcc.target/riscv/sat_u_sub-7.c: Ditto.
+	* gcc.target/riscv/sat_u_sub_imm-11.c: Ditto.
+	* gcc.target/riscv/sat_u_sub_imm-11_1.c: Ditto.
+	* gcc.target/riscv/sat_u_sub_imm-11_2.c: Ditto.
+	* gcc.target/riscv/sat_u_sub_imm-15.c: Ditto.
+	* gcc.target/riscv/sat_u_sub_imm-15_1.c: Ditto.
+	* gcc.target/riscv/sat_u_sub_imm-15_2.c: Ditto.
+	* gcc.target/riscv/sat_u_sub_imm-3.c: Ditto.
+	* gcc.target/riscv/sat_u_sub_imm-3_1.c: Ditto.
+	* gcc.target/riscv/sat_u_sub_imm-3_2.c: Ditto.
+	* gcc.target/riscv/sat_u_sub_imm-7.c: Ditto.
+	* gcc.target/riscv/sat_u_sub_imm-7_1.c: Ditto.
+	* gcc.target/riscv/sat_u_sub_imm-7_2.c: Ditto.
+
 2024-09-01  Hans-Peter Nilsson  <hp@axis.com>
 
 	* g++.dg/modules/modules.exp (module_do_it): Prune compilation