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| author | Richard Sandiford <rsandifo@redhat.com> | 2003-08-18 07:58:06 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2003-08-18 07:58:06 +0000 |
| commit | 4195786e34e0e5cc68b5fa09a583d562c0a58572 (patch) | |
| tree | 0600790fd024fe7be7b540870b424d0de319ffd2 /gcc | |
| parent | 6d4ede5fc2e335a76d7544cc068c05e733f97d9a (diff) | |
| download | gcc-4195786e34e0e5cc68b5fa09a583d562c0a58572.zip gcc-4195786e34e0e5cc68b5fa09a583d562c0a58572.tar.gz gcc-4195786e34e0e5cc68b5fa09a583d562c0a58572.tar.bz2 | |
mips.md (muldf3, mulsf3): Don't call a gen_* function.
* config/mips/mips.md (muldf3, mulsf3): Don't call a gen_* function.
(muldf3_internal, muldf3_r4300): Select based on TARGET_4300_MUL_FIX
rather than TARGET_MIPS4300.
(mulsf3_internal, mulsf3_r4300): Likewise.
From-SVN: r70534
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 56 |
2 files changed, 23 insertions, 40 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 84382a7..0460b1f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2003-08-18 Richard Sandiford <rsandifo@redhat.com> + * config/mips/mips.md (muldf3, mulsf3): Don't call a gen_* function. + (muldf3_internal, muldf3_r4300): Select based on TARGET_4300_MUL_FIX + rather than TARGET_MIPS4300. + (mulsf3_internal, mulsf3_r4300): Likewise. + +2003-08-18 Richard Sandiford <rsandifo@redhat.com> + * config/mips/mips.md: Renumber unspecs. Clean up comments. 2003-08-17 Roger Sayle <roger@eyesopen.com> diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 5a770b8..4e82958 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1360,87 +1360,63 @@ ;; .................... ;; -;; Early Vr4300 silicon has a CPU bug where multiplies with certain -;; operands may corrupt immediately following multiplies. This is a -;; simple fix to insert NOPs. - (define_expand "muldf3" [(set (match_operand:DF 0 "register_operand" "=f") (mult:DF (match_operand:DF 1 "register_operand" "f") (match_operand:DF 2 "register_operand" "f")))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" - " -{ - if (!TARGET_MIPS4300) - emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2])); - else - emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2])); - DONE; -}") + "") (define_insn "muldf3_internal" [(set (match_operand:DF 0 "register_operand" "=f") (mult:DF (match_operand:DF 1 "register_operand" "f") (match_operand:DF 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_MIPS4300" + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_4300_MUL_FIX" "mul.d\\t%0,%1,%2" [(set_attr "type" "fmul") (set_attr "mode" "DF")]) +;; Early VR4300 silicon has a CPU bug where multiplies with certain +;; operands may corrupt immediately following multiplies. This is a +;; simple fix to insert NOPs. + (define_insn "muldf3_r4300" [(set (match_operand:DF 0 "register_operand" "=f") (mult:DF (match_operand:DF 1 "register_operand" "f") (match_operand:DF 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_MIPS4300" - "* -{ - output_asm_insn (\"mul.d\\t%0,%1,%2\", operands); - if (TARGET_4300_MUL_FIX) - output_asm_insn (\"nop\", operands); - return \"\"; -}" + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_4300_MUL_FIX" + "mul.d\\t%0,%1,%2\;nop" [(set_attr "type" "fmul") (set_attr "mode" "DF") - (set_attr "length" "8")]) ;; mul.d + nop + (set_attr "length" "8")]) (define_expand "mulsf3" [(set (match_operand:SF 0 "register_operand" "=f") (mult:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "TARGET_HARD_FLOAT" - " -{ - if (!TARGET_MIPS4300) - emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2])); - else - emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2])); - DONE; -}") + "") (define_insn "mulsf3_internal" [(set (match_operand:SF 0 "register_operand" "=f") (mult:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && !TARGET_MIPS4300" + "TARGET_HARD_FLOAT && !TARGET_4300_MUL_FIX" "mul.s\\t%0,%1,%2" [(set_attr "type" "fmul") (set_attr "mode" "SF")]) +;; See muldf3_r4300. + (define_insn "mulsf3_r4300" [(set (match_operand:SF 0 "register_operand" "=f") (mult:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_MIPS4300" - "* -{ - output_asm_insn (\"mul.s\\t%0,%1,%2\", operands); - if (TARGET_4300_MUL_FIX) - output_asm_insn (\"nop\", operands); - return \"\"; -}" + "TARGET_HARD_FLOAT && TARGET_4300_MUL_FIX" + "mul.s\\t%0,%1,%2\;nop" [(set_attr "type" "fmul") (set_attr "mode" "SF") - (set_attr "length" "8")]) ;; mul.s + nop + (set_attr "length" "8")]) ;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while |