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authorUros Bizjak <ubizjak@gmail.com>2009-07-15 17:40:15 +0200
committerUros Bizjak <uros@gcc.gnu.org>2009-07-15 17:40:15 +0200
commit31f44cd09ad0001da1bf2e12fb18931a1c4142df (patch)
tree539001fccfff7fa46f036c571301e801d032b1f8 /gcc
parent1fba7394b093bf541afea220196183355927cfb2 (diff)
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sse.md (copysign<mode>3): Use "and-not" SSE instruction instead of "and" with inverted sign bit mask value.
* config/i386/sse.md (copysign<mode>3): Use "and-not" SSE instruction instead of "and" with inverted sign bit mask value. Use "nonimmediate_operand" for operand 1 and operand 2 predicate. Allocate registers only for operand 4 and operand 5. From-SVN: r149691
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog8
-rw-r--r--gcc/config/i386/sse.md20
2 files changed, 15 insertions, 13 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 812c794..b87b62a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,7 +1,9 @@
-2009-07-15 Uros Bizjak <ubizjak@gmail.com>
+2009-07-15 Uros Bizjak <ubizjak@gmail.com>
- * config/i386/sse.md (copysign<mode>3): Allocate registers only for
- operands[5] and operands[6].
+ * config/i386/sse.md (copysign<mode>3): Use "and-not" SSE instruction
+ instead of "and" with inverted sign bit mask value. Use
+ "nonimmediate_operand" for operand 1 and operand 2 predicate.
+ Allocate registers only for operand 4 and operand 5.
2009-07-15 Jakub Jelinek <jakub@redhat.com>
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index cde91e4..ce83029 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1595,21 +1595,21 @@
(set_attr "mode" "<MODE>")])
(define_expand "copysign<mode>3"
- [(set (match_dup 5)
- (and:SSEMODEF2P (match_operand:SSEMODEF2P 1 "register_operand" "")
- (match_dup 3)))
- (set (match_dup 6)
- (and:SSEMODEF2P (match_operand:SSEMODEF2P 2 "register_operand" "")
- (match_dup 4)))
+ [(set (match_dup 4)
+ (and:SSEMODEF2P
+ (not:SSEMODEF2P (match_dup 3))
+ (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")))
+ (set (match_dup 5)
+ (and:SSEMODEF2P (match_dup 3)
+ (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))
(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (ior:SSEMODEF2P (match_dup 5) (match_dup 6)))]
+ (ior:SSEMODEF2P (match_dup 4) (match_dup 5)))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
{
- operands[3] = ix86_build_signbit_mask (<ssescalarmode>mode, 1, 1);
- operands[4] = ix86_build_signbit_mask (<ssescalarmode>mode, 1, 0);
+ operands[3] = ix86_build_signbit_mask (<ssescalarmode>mode, 1, 0);
+ operands[4] = gen_reg_rtx (<MODE>mode);
operands[5] = gen_reg_rtx (<MODE>mode);
- operands[6] = gen_reg_rtx (<MODE>mode);
})
;; Also define scalar versions. These are used for abs, neg, and