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| author | Greta Yorsh <greta.yorsh@arm.com> | 2013-04-05 18:13:54 +0100 |
|---|---|---|
| committer | Greta Yorsh <gretay@gcc.gnu.org> | 2013-04-05 18:13:54 +0100 |
| commit | 2385b218b2157281f844a5f58239f15a6db49a33 (patch) | |
| tree | 7d1f82849d2652f388a6ac662464ee17e5ca8dd0 /gcc | |
| parent | 75fe1cb5dd734f87eb163b671cd69b2e3e4fd8ed (diff) | |
| download | gcc-2385b218b2157281f844a5f58239f15a6db49a33.zip gcc-2385b218b2157281f844a5f58239f15a6db49a33.tar.gz gcc-2385b218b2157281f844a5f58239f15a6db49a33.tar.bz2 | |
arm.md: Comment on splitting Thumb1 patterns.
2013-04-05 Greta Yorsh <Greta.Yorsh@arm.com>
* config/arm/arm.md: Comment on splitting Thumb1 patterns.
From-SVN: r197529
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 19 |
2 files changed, 23 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2bd27c3..9e0e5c9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2013-04-05 Greta Yorsh <Greta.Yorsh@arm.com> + * config/arm/arm.md: Comment on splitting Thumb1 patterns. + +2013-04-05 Greta Yorsh <Greta.Yorsh@arm.com> + * config/arm/arm.md (arm_smax_insn): Convert define_insn into define_insn_and_split. (arm_smin_insn,arm_umaxsi3,arm_uminsi3): Likewise. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 68519f4..a1789a2 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -22,6 +22,25 @@ ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. +;; Beware of splitting Thumb1 patterns that output multiple +;; assembly instructions, in particular instruction such as SBC and +;; ADC which consume flags. For example, in the pattern thumb_subdi3 +;; below, the output SUB implicitly sets the flags (assembled to SUBS) +;; and then the Carry flag is used by SBC to compute the correct +;; result. If we split thumb_subdi3 pattern into two separate RTL +;; insns (using define_insn_and_split), the scheduler might place +;; other RTL insns between SUB and SBC, possibly modifying the Carry +;; flag used by SBC. This might happen because most Thumb1 patterns +;; for flag-setting instructions do not have explicit RTL for setting +;; or clobbering the flags. Instead, they have the attribute "conds" +;; with value "set" or "clob". However, this attribute is not used to +;; identify dependencies and therefore the scheduler might reorder +;; these instruction. Currenly, this problem cannot happen because +;; there are no separate Thumb1 patterns for individual instruction +;; that consume flags (except conditional execution, which is treated +;; differently). In particular there is no Thumb1 armv6-m pattern for +;; sbc or adc. + ;;--------------------------------------------------------------------------- ;; Constants |