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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2024-01-19 16:34:25 +0800 |
|---|---|---|
| committer | Robin Dapp <rdapp@ventanamicro.com> | 2024-01-19 10:48:56 +0100 |
| commit | 01260a823073675e13dd1fc85cf2657a5396adf2 (patch) | |
| tree | 8f13abdba796930bb0581304e94bdd38cffb967e /gcc | |
| parent | 62b59bc4f70d02a485c527aa3277f4b4010edb6b (diff) | |
| download | gcc-01260a823073675e13dd1fc85cf2657a5396adf2.zip gcc-01260a823073675e13dd1fc85cf2657a5396adf2.tar.gz gcc-01260a823073675e13dd1fc85cf2657a5396adf2.tar.bz2 | |
RISC-V: Fix RVV_VLMAX
This patch fixes memory hog found in SPEC2017 wrf benchmark which caused by
RVV_VLMAX since RVV_VLMAX generate brand new rtx by gen_rtx_REG (Pmode, X0_REGNUM)
every time we call RVV_VLMAX, that is, we are always generating garbage and redundant
(reg:DI 0 zero) rtx.
After this patch fix, the memory hog is gone.
Time variable usr sys wall GGC
machine dep reorg : 1.99 ( 9%) 0.35 ( 56%) 2.33 ( 10%) 939M ( 80%) [Before this patch]
machine dep reorg : 1.71 ( 6%) 0.16 ( 27%) 3.77 ( 6%) 659k ( 0%) [After this patch]
Time variable usr sys wall GGC
machine dep reorg : 75.93 ( 18%) 14.23 ( 88%) 90.15 ( 21%) 33383M ( 95%) [Before this patch]
machine dep reorg : 56.00 ( 14%) 7.92 ( 77%) 63.93 ( 15%) 4361k ( 0%) [After this patch]
Test is running. Ok for trunk if I passed the test with no regresion ?
PR target/113495
gcc/ChangeLog:
* config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
(RVV_VUNDEF): Ditto.
* config/riscv/riscv-vsetvl.cc: Add timevar.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv-protos.h | 5 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv-vsetvl.cc | 2 |
2 files changed, 3 insertions, 4 deletions
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 7853b48..7fe26fc 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -299,10 +299,9 @@ void riscv_run_selftests (void); #endif namespace riscv_vector { -#define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM) +#define RVV_VLMAX regno_reg_rtx[X0_REGNUM] #define RVV_VUNDEF(MODE) \ - gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)), \ - UNSPEC_VUNDEF) + gen_rtx_UNSPEC (MODE, gen_rtvec (1, RVV_VLMAX), UNSPEC_VUNDEF) /* These flags describe how to pass the operands to a rvv insn pattern. e.g.: diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 2067073..54c85ff 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -3556,7 +3556,7 @@ const pass_data pass_data_vsetvl = { RTL_PASS, /* type */ "vsetvl", /* name */ OPTGROUP_NONE, /* optinfo_flags */ - TV_NONE, /* tv_id */ + TV_MACH_DEP, /* tv_id */ 0, /* properties_required */ 0, /* properties_provided */ 0, /* properties_destroyed */ |