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author | Thomas Preud'homme <thomas.preudhomme@arm.com> | 2018-04-11 10:07:25 +0000 |
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committer | Thomas Preud'homme <thopre01@gcc.gnu.org> | 2018-04-11 10:07:25 +0000 |
commit | 60d1915f9a3bbc2b3cc9d5eec72404d9b7180ad8 (patch) | |
tree | 895af22275d062d0cc9da1b374f5b5984846e6c6 /gcc | |
parent | 52556a878d77b0b6c8ad680c79d5a3db14503a42 (diff) | |
download | gcc-60d1915f9a3bbc2b3cc9d5eec72404d9b7180ad8.zip gcc-60d1915f9a3bbc2b3cc9d5eec72404d9b7180ad8.tar.gz gcc-60d1915f9a3bbc2b3cc9d5eec72404d9b7180ad8.tar.bz2 |
[ARM] Fix PR85261: ICE with FPSCR setter builtin
Instruction pattern for setting the FPSCR expects the input value to be
in a register. However, __builtin_arm_set_fpscr expander does not ensure
that this is the case and as a result GCC ICEs when the builtin is
called with a constant literal.
This commit fixes the builtin to force the input value into a register.
It also remove the unneeded volatile in the existing fpscr test and
fixes the function prototype.
2018-04-11 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
PR target/85261
* config/arm/arm-builtins.c (arm_expand_builtin): Force input operand
into register.
gcc/testsuite/
PR target/85261
* config/arm/arm-builtins.c (arm_expand_builtin): Force input operand
into register.
From-SVN: r259310
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 6 | ||||
-rw-r--r-- | gcc/config/arm/arm-builtins.c | 2 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 6 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arm/fpscr.c | 9 |
4 files changed, 19 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 846fc1e..9e1d6f8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-04-11 Thomas Preud'homme <thomas.preudhomme@arm.com> + + PR target/85261 + * config/arm/arm-builtins.c (arm_expand_builtin): Force input operand + into register. + 2018-04-10 Aaron Sawdey <acsawdey@linux.ibm.com> PR target/85321 diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 184eb2a..7fde7a0 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -2592,7 +2592,7 @@ arm_expand_builtin (tree exp, icode = CODE_FOR_set_fpscr; arg0 = CALL_EXPR_ARG (exp, 0); op0 = expand_normal (arg0); - pat = GEN_FCN (icode) (op0); + pat = GEN_FCN (icode) (force_reg (SImode, op0)); } emit_insn (pat); return target; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a311de0..9b224f5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2018-04-11 Thomas Preud'homme <thomas.preudhomme@arm.com> + + PR target/85261 + * config/arm/arm-builtins.c (arm_expand_builtin): Force input operand + into register. + 2018-04-10 Paolo Carlini <paolo.carlini@oracle.com> PR c++/70808 diff --git a/gcc/testsuite/gcc.target/arm/fpscr.c b/gcc/testsuite/gcc.target/arm/fpscr.c index 7b4d71d..4c3eaf7 100644 --- a/gcc/testsuite/gcc.target/arm/fpscr.c +++ b/gcc/testsuite/gcc.target/arm/fpscr.c @@ -6,11 +6,14 @@ /* { dg-add-options arm_fp } */ void -test_fpscr () +test_fpscr (void) { - volatile unsigned int status = __builtin_arm_get_fpscr (); + unsigned status; + + __builtin_arm_set_fpscr (0); + status = __builtin_arm_get_fpscr (); __builtin_arm_set_fpscr (status); } /* { dg-final { scan-assembler "mrc\tp10, 7, r\[0-9\]+, cr1, cr0, 0" } } */ -/* { dg-final { scan-assembler "mcr\tp10, 7, r\[0-9\]+, cr1, cr0, 0" } } */ +/* { dg-final { scan-assembler-times "mcr\tp10, 7, r\[0-9\]+, cr1, cr0, 0" 2 } } */ |