re PR lto/59326 (FAIL: gcc.dg/vect/vect-simd-clone-*.c)

	PR lto/59326
	* gcc.target/i386/i386.exp (check_effective_target_avx2): Move to...
	* lib/target-supports.exp (check_effective_target_avx2): ... here.
	(check_effective_target_vect_simd_clones): New.
	* gcc.dg/vect/vect-simd-clone-1.c: Add dg-require-effective-target
	vect_simd_clones.
	* gcc.dg/vect/vect-simd-clone-2.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-3.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-4.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-5.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-6.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-7.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-8.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-9.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-10.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-11.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-12.c: Likewise.

From-SVN: r205606

15 files changed, 70 insertions, 12 deletions

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f92967a..b9c2b6e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,23 @@
+2013-12-02  Jakub Jelinek  <jakub@redhat.com>
+
+	PR lto/59326
+	* gcc.target/i386/i386.exp (check_effective_target_avx2): Move to...
+	* lib/target-supports.exp (check_effective_target_avx2): ... here.
+	(check_effective_target_vect_simd_clones): New.
+	* gcc.dg/vect/vect-simd-clone-1.c: Add dg-require-effective-target
+	vect_simd_clones.
+	* gcc.dg/vect/vect-simd-clone-2.c: Likewise.
+	* gcc.dg/vect/vect-simd-clone-3.c: Likewise.
+	* gcc.dg/vect/vect-simd-clone-4.c: Likewise.
+	* gcc.dg/vect/vect-simd-clone-5.c: Likewise.
+	* gcc.dg/vect/vect-simd-clone-6.c: Likewise.
+	* gcc.dg/vect/vect-simd-clone-7.c: Likewise.
+	* gcc.dg/vect/vect-simd-clone-8.c: Likewise.
+	* gcc.dg/vect/vect-simd-clone-9.c: Likewise.
+	* gcc.dg/vect/vect-simd-clone-10.c: Likewise.
+	* gcc.dg/vect/vect-simd-clone-11.c: Likewise.
+	* gcc.dg/vect/vect-simd-clone-12.c: Likewise.
+
 2013-12-02  Bernd Edlinger  <bernd.edlinger@hotmail.de>
 
 	* gcc.dg/pr56997-4.c: New testcase.
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c
index d802dfb..9fdd056 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-10.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-10.c
index 3f29b52..923a945 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-10.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-10.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 /* { dg-additional-sources vect-simd-clone-10a.c } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-11.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-11.c
index 4cccf85..a04530e2 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-11.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-11.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-12.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-12.c
index 5c94153..279abd7 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-12.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-12.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 /* { dg-additional-sources vect-simd-clone-12a.c } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c
index 4447607..0eae49d 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c
index 222d88e..857c6f7 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c
index 5b0a93a..c64f1b0 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c
index fd1d5ff..1d2b067 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c
index 5e56414..26995da 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c
index 24856ea..2745c5e 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c
index 19c25c9..e0b09b6 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-9.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-9.c
index 95156b9..0c5ff4f 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-9.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-9.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 
diff --git a/gcc/testsuite/gcc.target/i386/i386.exp b/gcc/testsuite/gcc.target/i386/i386.exp
index 15f744c..c7c2676 100644
--- a/gcc/testsuite/gcc.target/i386/i386.exp
+++ b/gcc/testsuite/gcc.target/i386/i386.exp
@@ -209,18 +209,6 @@ proc check_effective_target_lzcnt { } {
     } "-mlzcnt" ]
 }
 
-# Return 1 if avx2 instructions can be compiled.
-proc check_effective_target_avx2 { } {
-    return [check_no_compiler_messages avx2 object {
-	typedef long long __v4di __attribute__ ((__vector_size__ (32)));
-	__v4di
-	mm256_is32_andnotsi256  (__v4di __X, __v4di __Y)
-        {
-	   return __builtin_ia32_andnotsi256 (__X, __Y);
-	}
-    } "-O0 -mavx2" ]
-}
-
 # Return 1 if bmi instructions can be compiled.
 proc check_effective_target_bmi { } {
     return [check_no_compiler_messages bmi object {
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 104818d..e0f097d 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2146,6 +2146,32 @@ proc check_effective_target_vect_floatuint_cvt { } {
     return $et_vect_floatuint_cvt_saved
 }
 
+# Return 1 if the target supports #pragma omp declare simd, 0 otherwise.
+#
+# This won't change for different subtargets so cache the result.
+
+proc check_effective_target_vect_simd_clones { } {
+    global et_vect_simd_clones_saved
+
+    if [info exists et_vect_simd_clones_saved] {
+	verbose "check_effective_target_vect_simd_clones: using cached result" 2
+    } else {
+	set et_vect_simd_clones_saved 0
+	if { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
+	    # On i?86/x86_64 #pragma omp declare simd builds a sse2, avx and
+	    # avx2 clone.  Only the right clone for the specified arch will be
+	    # chosen, but still we need to at least be able to assemble
+	    # avx2.
+	    if { [check_effective_target_avx2] } {
+		set et_vect_simd_clones_saved 1
+	    }
+	}
+    }
+
+    verbose "check_effective_target_vect_simd_clones: returning $et_vect_simd_clones_saved" 2
+    return $et_vect_simd_clones_saved
+}
+
 # Return 1 if this is a AArch64 target supporting big endian
 proc check_effective_target_aarch64_big_endian { } {
     return [check_no_compiler_messages aarch64_big_endian assembly {
@@ -5106,6 +5132,18 @@ proc check_effective_target_avx { } {
     } "-O2 -mavx" ]
 }
 
+# Return 1 if avx2 instructions can be compiled.
+proc check_effective_target_avx2 { } {
+    return [check_no_compiler_messages avx2 object {
+	typedef long long __v4di __attribute__ ((__vector_size__ (32)));
+	__v4di
+	mm256_is32_andnotsi256  (__v4di __X, __v4di __Y)
+        {
+	   return __builtin_ia32_andnotsi256 (__X, __Y);
+	}
+    } "-O0 -mavx2" ]
+}
+
 # Return 1 if sse instructions can be compiled.
 proc check_effective_target_sse { } {
     return [check_no_compiler_messages sse object {